ics95v847 Integrated Device Technology, ics95v847 Datasheet

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ics95v847

Manufacturer Part Number
ics95v847
Description
2.5v Wide Range Frequency Clock Driver 45mhz - 233mhz
Manufacturer
Integrated Device Technology
Datasheet

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2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
Product Description/Features:
Switching Characteristics:
Functionality
0718E—11/24/08
A
n (
n (
G
G
2
2
V
5 .
5 .
o
o
N
N
D
m
m
V
V
D
D
D
)
)
Zero Delay Board Fan Out, SO-DIMM
Provides complete DDR registered DIMM solution
with ICSSSTV16857, ICSSSTV16859 or
ICSSSTV32852
Low skew, low jitter PLL clock driver
1 to 5 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
CYCLE - CYCLE jitter: <60ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: ±30ps
DUTY CYCLE: 49.5% - 50.5%
C
L
K
N I
L
H
L
H
_
P
N I
U
T
T
S
C
L
K
H
H
L
L
_
Integrated
Circuit
Systems, Inc.
N I
C
C
L
H
H
L
L
K
T
C
L
H
L
H
L
K
C
O
F
U
B
T
_
P
O
L
H
L
H
U
U
T
T
S
T
F
B
_
O
H
L
H
L
U
T
C
B
B
P
y
y
p
p
L
a
a
L
s s
s s
o
o
S
n
n
e
e
a t
d
d
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f f
f f
Block Diagram
CLK_INC
CLK_INT
FB_INC
FB_INT
CLK_INC
CLK_INT
CLKC0
CLKC1
CLKT0
CLKT1
AGND
AVDD
GND
GND
VDD
VDD
4.40 mm. Body, 0.65 mm. pitch
Pin Configuration
PLL
24-Pin TSSOP
10
11
12
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
ICS95V847
CLKT4
CLKC4
CLKC3
CLKT3
VDD
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT2
CLKC2
GND
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4

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ics95v847 Summary of contents

Page 1

... FB_INT FB_INC CLK_INC CLK_INT ICS95V847 Pin Configuration GND 1 24 CLKT4 CLKC0 2 23 CLKC4 CLKT0 3 22 CLKC3 GND 4 21 CLKT3 VDD 5 20 VDD CLK_INT 6 19 FB_INT CLK_INC 7 18 ...

Page 2

... C This PLL Clock Buffer is designed for a V ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog power input (AV ) ...

Page 3

... GND 0pf @ 200MHz 0pf 2.7V, Vout = GND V = 2.3V Iin = -18mA - = GND ICS95V847 + 0.5V MIN TYP MAX UNITS 5 µA 5 µA 148 mA 100 µA ±10 mA -1.2 - 0.1 DD 1.7V 0.1 0.6 2.5 3 ...

Page 4

... ICS95V847 Recommended Operating Condition (see note1 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage Low level input voltage V IL High level input voltage input signal voltage V IN (note 2) Differential input signal V ID voltage (note 3) ...

Page 5

... PLH 1 CLK_IN to any output t PLL t PD# to any output EN tdis PD# to any output T 100MHz to 200MHz jit (per) 100MHz to 200MHz t sl(i) t sl(o) -T 100MHz to 200MHz cyc cyc 4 T skew 5 ICS95V847 MIN MAX UNITS 45 233 MHz 95 210 MHz µs MIN TYP MAX UNITS 5 ...

Page 6

... VDD/2 ICS95V847 -VDD/2 NOTE: V (TT) = GND Y , FBOUTC FBOUTT X 0718E—11/24/08 Parameter Measurement Information (CLKC) V (CLKC) ICS95V847 GND Figure 1. IBIS Model Output Load -VDD -VDD/2 Figure 2. Output Load Test Circuit t c(n) t jit(cc c(n) ± t c(n+1) Figure 3. Cycle-to-Cycle Jitter ...

Page 7

... Y , FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0718E—11/24/08 Parameter Measurement Information large number of samples) Figure 4. Static Phase Offset t (SK_O) Figure 5. Output Skew (jit_per) C( Figure 6. Period Jitter 7 ICS95V847 n+1 ...

Page 8

... ICS95V847 Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0718E—11/24/08 Parameter Measurement Information t (hper_n) t (hper_n+ (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% Rise t sl Fall t sl Figure 8. Input and Output Slew Rates 8 80 20% ...

Page 9

... aaa VARIATIONS - SEATING SEATING PLANE PLANE 24 aaa C Reference Doc.: JEDEC Publication 95, MO-153 10-0035 G = TSSOP 9 ICS95V847 In Millimeters In Inches MIN MAX MIN -- 1.20 -- 0.05 0.15 .002 0.80 1.05 .032 0.19 0.30 .007 0.09 0.20 .0035 SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC 4.30 4.50 .169 0.65 BASIC 0.0256 BASIC ...

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