ICS950410AFLFT IDT, Integrated Device Technology Inc, ICS950410AFLFT Datasheet - Page 8

• Manufacturer Part Number: ICS950410AFLFT
• Description: IC SYSTEM CLK CHIP AMD-K8 48SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS950410AFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 300MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 300MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950410AFLFT

ICS950410
Preliminary Product Preview
0888A—04/22/05
I
I
I
I
2
2
2
2
C Table: Skew Control Register
C Table: WD Time Control & Async Frequency Selection Register
C Table: VCO Control Select Bit & WD Timer Control Register
C Table: VCO Frequency Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 10
Byte 11
Byte 8
Byte 9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
REF1 Strength
PCI/HTTSkw3
PCI/HTTSkw2
PCI/HTTSkw1
PCI/HTTSkw0
WDStatus
Reserved
PCISkw3
PCISkw2
PCISkw1
PCISkw0
WDTCtrl
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
M/NEN
WDEN
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Name
Name
Name
Name
ASEL
WD2
WD1
WD0
AEN
M Divider Programming
AGP/PCI/ Freq Source
CPU-PCI 7 Step Skew
REF1 strength control
Watch Dog Time base
Watch Dog Safe Freq
CPU-PCI/HTT 7 Step
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Control Function
Control Function
Control Function
Skew Control (ps)
Async Frequency
M/N Programming
Watchdog Enable
Programming bits
WD Alarm Status
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Control (ps)
Reserved
bits (5:0)
Control
Enable
Select
Select
8
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
The decimal representation of N Divider in
VCO Frequency = 14.318 x [NDiv(9:0)+8]
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
the watchdog timer waits before it goes to
These bits represent X*290ms (or 1.16S)
Divier in Byte 11 and 12 will configure the
Writing to these bit will configure the safe
alarm mode. Default is 7 X 290ms = 2s.
0000:0
0000:0
The decimal representation of M and N
VCO frequency. Default at power up =
290ms Base
FIX PLL
Disable
Disable
66MHz
Normal
frequency as Byte0 bit (4:0).
latch-in or Byte 0 Rom table.
1x
0
0
0
0
-
0100:150 1000:300 1100:450
0100:150 1000:300 1100:450
Byte 11 and 12
/ [MDiv(5:0)+2]
1160ms Base
75.4MHz
CPU PLL
Enable
Enable
Alarm
2x
1
1
1
1
-
PWD
PWD
PWD
PWD
1
1
0
0
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X