87946AYI-147 IDT, Integrated Device Technology Inc, 87946AYI-147 Datasheet - Page 7

• Manufacturer Part Number: 87946AYI-147
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 87946AYI-147

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

ICS87946I-147 Data Sheet
Table 5B. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from V
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at V
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
ICS87946AYI-147 REVISION A AUGUST 7, 2009
Symbol
f
t
tsk(b)
tsk(o)
tsk(w)
tsk(pp)
t
t
t
t
MAX
PD
R
PW
EN
DIS
/ t
F
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Bank Skew, NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew;
NOTE 4, 7
Part-to-Part Skew;
NOTE 5, 7
Output Rise/Fall Time;
NOTE 6
Output Pulse Width
Output Enable Time;
NOTE 6
Output Disable Time;
NOTE 6
DD
/2 of the input to V
DD
= 3.3V ± 5%, V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
Measured on rising edge at V
DDX
/2 of the output.
Test Conditions
20% to 80%
ƒ ≤ 250MHz
DDA
ƒ = 10MHz
ƒ = 10MHz
= V
DDB
= V
7
DDX
DDC
/2.
DDX
DDX
DDX
DDX
= 2.5V ± 5%, T
/2
/2
/2
/2
t
PERIOD
Minimum
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
400
2
/2 - 1
A
= -40°C to 85°C
t
PERIOD
Typical
©2009 Integrated Device Technology, Inc.
/2
t
PERIOD
Maximum
250
175
200
875
950
35
5
3
3
/2 + 1
DDX
/2.
Units
MHz
ns
ps
ps
ps
ps
ps
ns
ns
%