87946AYI-147 IDT, Integrated Device Technology Inc, 87946AYI-147 Datasheet - Page 2

• Manufacturer Part Number: 87946AYI-147
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 87946AYI-147

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

ICS87946I-147 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS87946AYI-147 REVISION A AUGUST 7, 2009
8, 11, 15, 20,
Symbol
C
C
R
R
R
OUT
24, 27, 31
IN
PD
PULLUP
PULLDOWN
9, 13, 17
Number
10, 12,
14, 16
18, 22
21, 23
25, 29
28, 30
3, 4
19,
26,
32
1
2
5
6
7
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
CLK0, CLK1
QC0, QC1,
DIV_SELA
DIV_SELB
DIV_SELC
QC2, QC3
QB1, QB0
QA1, QA0
CLK_SEL
MR/nOE
Name
V
V
GND
QB2,
V
QA2,
V
DDC
DDB
DDA
DD
Output
Output
Output
Power
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
V
DD
= V
Description
Clock select input. When HIGH, selects CLK1.
When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Positive supply pin.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs. See Table 3
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs. See Table 3.
LVCMOS/LVTTL interface levels.
Power supply ground.
Output supply pins for Bank C outputs.
Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels.
7
Output supply pins for Bank B outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
7
Output supply pins for Bank A outputs.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
7
Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH, the
internal dividers are reset and the outputs are (High-Impedance). When logic
LOW, the internal dividers and the outputs are enabled. See Table 3.
LVCMOS/LVTTL interface levels.
DDA
Test Conditions
Ω
Ω
Ω
typical output impedance.
typical output impedance.
typical output impedance.
= V
DDB
2
= V
DDC
= 3.6V
LOW SKEW, ÷1, ÷2 LVCMOS/LVTTL CLOCK GENERATOR
Minimum
©2009 Integrated Device Technology, Inc.
Typical
25
51
51
7
Maximum
4
Units
k
k
pF
pF
Ω
Ω
Ω