ICS87946AYI-01LFT IDT, Integrated Device Technology Inc, ICS87946AYI-01LFT Datasheet

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ICS87946AYI-01LFT

Manufacturer Part Number
ICS87946AYI-01LFT
Description
IC CLOCK GENERATOR 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Clock Generatorr
Datasheet

Specifications of ICS87946AYI-01LFT

Pll
No
Input
CML, LVPECL, SSTL
Output
LVCMOS, LVTTL
Number Of Circuits
1
Ratio - Input:output
1:10
Differential - Input:output
Yes/No
Frequency - Max
250MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
250MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
87946AYI-01LFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS87946AYI-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
Description
CML, or SSTL input levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased from 10
to 20 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset input, MR/OE,
resets the internal frequency dividers and also controls the active
and high impedance states of all outputs.
The ICS87946I-01 is characterized at 3.3V core/3.3V output and
3.3V core/2.5V output. Guaranteed bank, output and part-to-part
skew characteristics make the ICS87946I-01 ideal for those clock
distribution applications demanding well defined performance and
repeatability.
Block Diagram
IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER
DIV_SELA
DIV_SELB
DIV_SELC
HiPerClockS™
ICS
MR/OE
PCLK
PCLK
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
The ICS87946I-01 is a low skew, ÷1, ÷2 Clock
Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS87946I-01 has one LVPECL clock input
pair. The PCLK/PCLK pair can accept LVPECL,
÷2
÷1
0
1
0
1
0
0
1
1
3
3
4
QA0:QA2
QB0:QB2
QC0:QC3
1
Features
Ten single ended LVCMOS/LVTTL outputs,
7Ω typical output impedance
LVPECL clock input pair
PCLK/PCLK supports the following input levels:
LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 120ps (maximum)
Part-to-part skew: 700ps (maximum)
Multiple frequency skew: 320ps (maximum)
Additive phase jitter, RMS: 0.19ps (typical)
3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C
ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
DIV_SELA
DIV_SELB
DIV_SELC
PCLK
PCLK
GND
V
nc
DD
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
7mm x 7mm x 1.45mm
9
10 11 12 13 14 15 16
32-Lead LQFP
package body
ICS87946I-01
Y Package
Top View
ICS87946AYI-01 REV. BMAY 4, 2007
ICS87946I-01
24
23
22
21
20
19
18
17
GND
QB0
V
GND
QB2
V
V
QB1
DDB
DDB
DDC

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ICS87946AYI-01LFT Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment 3 QA0:QA2 PCLK PCLK DIV_SELA DIV_SELB 3 QB0:QB2 DIV_SELC 4 QC0:QC3 1 ICS87946I- GND ICS87946I-01 32-Lead LQFP 7mm x 7mm x 1.45mm package body Y Package Top View ICS87946AYI-01 REV. BMAY 4, 2007 GND QB0 V DDB QB1 GND QB2 V DDB V DDC ...

Page 2

... When logic LOW, Pulldown the internal dividers and the outputs are enabled. See Table 3. LVCMOS/LVTTL interface levels. Test Conditions DDA DDB DDC 3.465V 2 Minimum Typical Maximum ICS87946AYI-01 REV. BMAY 4, 2007 Units pF pF Ω k Ω k Ω ...

Page 3

... Rating 4.6V -0. 0.5V DD -0. 0.5V DDx 47.9°C/W (0 lfpm) -65°C to 150°C = 3.3V ± 5 -40°C to 85°C DDC A Minimum Typical Maximum 3.135 3.3 3.135 3.3 ICS87946AYI-01 REV. BMAY 4, 2007 QC0:QC3 Hi-Z Active Active Active Active fIN/1 fIN/2 Units 3.465 V 3.465 ...

Page 4

... Typical Maximum 3.135 3.3 3.465 2.375 2.5 2.625 Minimum Typical Maximum -0.3 -5 2.6 -5 Minimum Typical Maximum 150 -5 -150 0.3 1.0 GND + 1.5 V ICS87946AYI-01 REV. BMAY 4, 2007 Units Units + 0.3 V 0.8 V 150 µA µA V 0.5 V µA 5 µA Units µA 5 µA µA µA ...

Page 5

... DDX /2 DDX 0.19 400 40 50 /2. DDX = 2.5V ± 5 -40°C to 85°C A Minimum Typical 2.5 3.2 /2 DDX /2 DDX /2 DDX /2 DDX 0.19 350 40 50 ICS87946AYI-01 REV. BMAY 4, 2007 Maximum Units 250 MHz 3 130 ps 320 ps 700 ps ps 950 /2. DDX Maximum Units 250 MHz 3 ...

Page 6

... Additive Phase Jitter @ 125MHz 12kHz to 20MHz = 0.19ps (typical) Offset Frequency (Hz) meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 6 ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 7

... IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER 2.05V±5% 1.25V±5% SCOPE DDA DDB, LVCMOS -1.25V±5% 3.3V/2.5V Output Load AC Test Circuit Qx V CMR Qy Output Skew QBx, QCx QAx Multiple Frequency Skew DDC GND V DDx 2 V DDx 2 tsk(o) tsk(ω) ICS87946AYI-01 REV. BMAY 4, 2007 SCOPE ...

Page 8

... Part-to-Part Skew 80% 20% Clock t Outputs R Output Rise/Fall Time IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER PCLK PCLK QAx, QBx, QCx Propagation Delay 80% QAx, QBx, QCx 20 Output Duty Cycle/Pulse Width/Period 8 V DDx DDx PERIOD 100% odc = t PERIOD ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 9

... R2/R1 = 0.609. IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER O : UTPUTS LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input PCLK V_REF nPCLK C1 0. ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 10

... Zo = 50Ω 3.3V LVPECL 50Ω 100 - 200 100 - 200 125 a 3.3V LVPECL Driver with AC Couple 3. 50Ω 100 Zo = 50Ω LVDS a 3.3V LVDS Driver ICS87946AYI-01 REV. BMAY 4, 2007 3.3V PCLK nPCLK HiPerClockS PCLK/nPCLK 3. PCLK nPCLK HiPerClockS PCLK/nPCLK R2 125 3. PCLK nPCLK HiPerClockS PCLK/nPCLK ...

Page 11

... NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS87946I-01 is: 1204 IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER θ vs. Air Flow JA 0 200 67.8°C/W 55.9°C/W 47.9°C/W 42.1°C/W 11 500 50.1°C/W 39.4°C/W ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 12

... D & E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ 16:1, SINGLE-ENDED MULTIPLEXER Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 12 ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 13

... Shipping Packaging 32 Lead LQFP 32 Lead LQFP 1000 Tape & Reel “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP 1000 Tape & Reel 13 Temperature Tray -40°C to 85°C -40°C to 85°C Tray -40°C to 85°C -40°C to 85°C ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 14

... AC Characteristics Tables - added Additive Phase Jitter row. Added Additive Phase Jitter section. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Part/Order Number and Note. Updated format throughout the datasheet. 14 Date 5/4/07 ICS87946AYI-01 REV. BMAY 4, 2007 ...

Page 15

ICS87946I-01 LOW SKEW, ÷1, ÷2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United ...

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