SSTV16857MTDX Fairchild Semiconductor, SSTV16857MTDX Datasheet
SSTV16857MTDX
Specifications of SSTV16857MTDX
Related parts for SSTV16857MTDX
SSTV16857MTDX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Preliminary) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Compliant with DDR-I registered module specifications r Operates at 2 ...
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Functional Description The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. When the LV-CMOS RESET signal is asserted LOW, ...
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Absolute Maximum Ratings Supply Voltage (V ) DDQ Supply Voltage ( Reference Voltage (V ) REF Input Voltage ( Output Voltage ( Outputs Active (Note 2) 0. ...
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DC Electrical Characteristics (SSTV16857) Symbol Parameter I Dynamic Operating Current DDD Clock Only Dynamic Operating Current per Data Input R Output HIGH On Resistance OH R Output LOW On Resistance ...
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AC Electrical Characteristics (SSTV16857) Symbol Parameter f Maximum Clock Frequency MAX t Pulse Duration, CK, CK HIGH or LOW (Figure Differential Inputs Activation Time, ACT (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) ...
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Capacitance (Note 15) Symbol Parameter C Data Pin Input Capacitance IN CK Input Capacitance RESET q Note 15 MHz, Capacitance is characterized but not tested Loading and Waveforms Note: C ...
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Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to ...