SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 33

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Clock Driver Characteristics at Application Frequency (frequency band 1)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
t
1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This
parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between
Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered
as a design goal only.
2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package
routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn
output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related
to simultaneous switching noise (SSO).
3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on t
t
t
t
BAND
t
t
JIT
t
PWH/PWL
Symbol
t
DYNOFF 6
JIT
JIT
JIT
t
STAOFF
t
t
t
QSK
FDYN
CKSK
STAB
(
(
(
(
HPER
CC
PER
CC
1
+)
-)
2
)
) Half period jitter
Cycle-to-cycle period
jitter
Cycle-to-cycle period
jitter
Stabilization time
Dynamic phase offset
Fractional Clock Output
skew
Yn Clock Period jitter
Yn pulse width
HIG/LOW duration
Qn Output to Yn clock
tolerance (Standard
1/2-Clock Pre-Launch)
Average delay through
the register beween the
input clock and output
clock.
operation)
Maximum variation in
delay between the input
& output clock
SSC modulation
frequency
SSC clock input
frequency deviation
PLL Loop bandwidth
(-3 dB from unity gain)
1
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
5
Parameter
. (1.25V
2
t
It
to 1/2t
It
Output
Inversion
enabled
Output
Inversion
disabled
Standard
1/2-Clock
Pre-Launch
t
+ 1/2 t
PW
STAOFF
JIT
JIT
Conditions
(hper)minI
(hper)maxI
= 1/2t
CK
CK
= t
-
CK
PDM
-
1.200
DDR3U-800
-100
-100
Min
0.00
-40
-50
-40
-50
25
1.9
30
0
-
-
-
7
1.300
Max
2.60
200
300
160
-0.5
40
50
15
40
50
33
0
6
DDR3U-1066
0.888
-100
-100
Min
1.59
0.00
-40
-50
-40
-50
30
30
0
-
-
-
7
0.988
Max
1.29
200
300
130
-0.5
40
15
40
50
33
33
50
0
6
DDR3U-1333
0.700
Min
-100
-100
1.40
0.00
-40
-40
-50
35
-50
30
0
-
-
-
7
0.800
Max
2.10
-0.5
200
300
110
333
COMMERCIAL TEMPERATURE RANGE
40
50
15
40
50
0
6
SSTE32882KA1
DDR3U-1600 Unit
0.585
Min
-100
-100
1.28
0.00
40
-30
-40
-30
-40
30
0
-
-
-
7
(DDR3U 1.25V)
0.665
Max
1.98
-0.5
100
200
30
40
10
30
40
90
33
0
6
-
MHz
kHz
ps
ps
µs
ps
ps
ps
ps
ns
ps
ns
ps
%
PW
7314/8
.