SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 3

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

Block Diagram - Register and PLL Logic Diagram (Positive Logic)
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]
indicates all of the chip select outputs.
DA0-DA2,
DA10, DA12,
DRAS, DCAS,
DWE
DA3..DA9,
DA11,
DA13..DA15,
DBA0..DBA2
V
REF
DCS[n:0]
DCKE0,
DCKE1
DODT0,
DODT1
RESET
CK
CK
FBIN
FBIN
(1)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
10KΩ~100KΩ
DRAS
DCAS
DWE
CS
Logic
DA0..DA2, DBA2
DA3, DA4, DBA0, DBA1
D
R
D
R
D
R
D
R
D
R
CE
CE
Q
Q
Q
Q
Q
PLL
1/4 CK
delay
1/4 CK
delay
1/4 CK
delay
0
1
0
1
1/4 CK
delay
3
4
0
1
0
1
Output
Inversion
Control Word
State Machine and
Control Logic
0
1
CMR
Access
3
Pre-
Launch
Enable
B-Enable
A-Enable
Y0..Y3-
OE0
4
OE2
OE3
OE1
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
QxA3..QxA9,
QxA11,
QxA13..QxA15,
QxBA0..QxBA2
QxA0-QxA2,
QxA10,
QxA12,
QxRAS,
QxCAS,
QxWE
QxCS[n:0]
QACKEn
QBCKEn
QAODTn
QBODTn
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
FBOUT
FBOUT
(1)
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