MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 6

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

General Description
Functional Overview
Figure 1:
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
Block Diagram
The MT9P031 sensor can be operated in its default mode or programmed by the user for
frame size, exposure, gain setting, and other parameters. The default mode outputs a full
resolution image at 15 frames per second (fps).
An on-chip analog-to-digital converter (ADC) provides 12 bits per pixel. FRAME_VALID
(FV) and LINE_VALID (LV) signals are output on dedicated pins, along with a pixel clock
that is synchronous with valid data.
The MT9P031produces extraordinarily clear, sharp digital pictures, and its ability to
capture both continuous video and single frames makes it the perfect choice for a wide
range of consumer and industrial applications, including cell phones, digital still
cameras, digital video cameras, and PC cameras.
The MT9P031 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between 6 and 27 MHz. The maximum
pixel rate is 96 Mp/s, corresponding to a clock rate of 96 MHz. Figure 1 illustrates a block
diagram of the sensor.
User interaction with the sensor is through the two-wire serial bus, which communi-
cates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 5Mp active-pixel array. The timing and control circuitry sequences through
the rows of the array, resetting and then reading each row in turn. In the time interval
between resetting a row and reading that row, the pixels in the row integrate incident
light. The exposure is controlled by varying the time interval between reset and readout.
Once a row has been read, the data from the columns is sequenced through an analog
signal chain (providing offset correction and gain), and then through an ADC. The
output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes
through a digital processing signal chain (which provides further data path corrections
and applies digital gain). The pixel data are output at a rate of up to 96 Mp/s, in addition
to frame and line synchronization signals.
STANDBY_BAR
RESET_BAR
TRIGGER
EXTCLK
OE
Analog Signal Chain
2752H x 2004V
Pixel Array
6
MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
Data Path
Aptina reserves the right to change products or specifications without notice.
Interface
Serial
©2005 Aptina Imaging Corporation. All rights reserved.
General Description
SCLK
S
S
PIXCLK
D
LV
FV
STROBE
DATA
ADDR
OUT
[11:0]