MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 18

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Stop Bit
Slave Address
Data Bit Transfer
Acknowledge Bit
No-Acknowledge Bit
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1
bit of direction. A “0” in the LSB (least significant bit) of the address indicates write mode
(0xBA), and a “1” indicates read mode (0xBB).
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is trans-
ferred 8 bits at a time, followed by an acknowledge bit.
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
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MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
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©2005 Aptina Imaging Corporation. All rights reserved.
Serial Bus Description