MT9P031I12STM-ES Aptina LLC, MT9P031I12STM-ES Datasheet - Page 27

• Manufacturer Part Number: MT9P031I12STM-ES
• Manufacturer: Aptina LLC

Specifications of MT9P031I12STM-ES

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 13:
PDF: 09005aef81a4a477/Source: 09005aef81a4a495
MT9P031_DS - Rev. E 7/10 EN
Reg. #
R0x00D
R0x00A
R0x00B
R0x00C
R10:0
R11:0
R12:0
R13:0
Bits
A negative adjustment to the effective shutter width in ACLKs. See Shutter_Width_Lower. Writes are synchronized to frame
boundaries. Affected by Synchronize_Changes. Legal values: [0, 8191].
15:0
Setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state and cause it to halt.
Clearing this bit will resume normal operation. This is equivalent to pulling RESET_BAR LOW, except that the two-wire serial
interface remains functional.
14:11
15:0
10:8
15:0
15:3
15:0
Register Description (continued)
6:0
15
7
2
1
0
Default
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
X
X
X
Name
Pixel Clock Control (RW)
Invert Pixel Clock
When set, LV, FV, and D_OUT should be captured on the rising edge of PIXCLK. When clear, they should
be captured on the falling edge. This is accomplished by inverting the PIXCLK output.
NOTE: This field is not reset by the soft Reset (R13).
Reserved
Shift Pixel Clock
Two's complement value representing how far to shift the PIXCLK output pin relative to D
EXTCLK cycles. Positive values shift PIXCLK later in time relative to D
internal array/datapath clock). No effect unless PIXCLK is divided by Divide Pixel Clock.
NOTE: This field is not reset by the soft Reset (R13).
Legal values: [-2, 2].
Reserved
Divide Pixel Clock
Produces a PIXCLK that is divided by the value times two. The value must be zero or a power of 2. This
will slow down the internal clock in the array control and datapath blocks, including pixel readout. It
will not affect the two-wire serial interface clock. A value of “0” corresponds to a PIXCLK with the same
frequency as EXTCLK. A value of 1 means f_PIXCLK = (f_EXTCLK / 2); 2 means f_PIXCLK = (f_EXTCLK / 4);
64 means f_PIXCLK = (f_EXTCLK / 128); and so on.
NOTE: This field is not reset by the soft Reset (R13). This field should not be written while in streaming
mode. Instead, Pause_Restart should be used to suspend output while the divider is being changed.
Legal values: [0, 1, 2, 4, 8, 16, 32, 64].
Restart (RW)
Reserved
Trigger
Setting this bit in Snapshot mode will cause the next trigger to occur as if the TRIGGER pin were
properly asserted/negated. Ineffective if not in Snapshot mode. The sense of this bit is NOT affected by
Invert Trigger.
When using this bit instead of the TRIGGER pin, make sure that either the trigger pin is continuously
asserted, or that the pad is continuously negated and Invert_Trigger is set.
Pause Restart
When set, Restart will not automatically be cleared. Instead, the sensor will pause at row 0 after Restart
is set. When Pause_Restart is cleared, the sensor will resume. This allows for a repeatable delay from
clearing restart to FV. When clearing this bit, be sure not to clear Restart as well: it will be cleared
automatically when the device has restarted.
Restart
Setting this bit will cause the sensor to abandon the current frame and restart from the first row. It will
take up to 2 * t_ROW for the restart to take effect. This bit resets to 0 automatically unless
Pause_Restart is set. Manually setting this bit to zero will cause undefined behavior.
Volatile.
Shutter Delay (RW)
Reset (RW)
27
MT9P031: 1/2.5-Inch 5Mp Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
OUT
(and thus relative to the
©2005 Aptina Imaging Corporation. All rights reserved.
OUT
Registers
, in