CY7C374-100AC Cypress Semiconductor Corp, CY7C374-100AC Datasheet - Page 6

• Manufacturer Part Number: CY7C374-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C374-100AC

• Family Name: FLASH370
• # Macrocells: 128
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• In System Programmable: No
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

POLARITY INPUT
Dedicated/Clock Inputs
Six pins on each member of the F
ed as input-only. There are two types of dedicated inputs on
F
illustrates the architecture for input pins. Four input options are
available for the user: combinatorial, registered, double-regis-
tered, or latched. If a registered or latched option is selected,
any one of the input clocks can be selected for control.
Figure 7 illustrates the architecture of input/clock pins. There
are either two or four input/clock pins available, depending on
the device selected. (The CY7C371 and CY7C372 have two
input/clock pins while the other devices have four input/clock
pins.) Like the input pins, input/clock pins can be combinatori-
al, registered, double registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input is user-configurable in polarity. The po-
Notes:
2.
3.
4.
LASH
FROM CLOCK
CLOCK PINS
C9 is not used on the CY7C371 and CY7C372.
C8 and C9 are not included on the CY7C371 and CY7C372 since each input/clock pin has the other input/clock pin as its clock.
C15 and C16 are not used on the CY7C371 and CY7C372 since there are two clocks.
370 devices: input pins and input/clock pins. Figure 6
C8
INPUT/CLOCK PIN
0
1
2
3
[3]
POLARITY MUXES
C9
FROM CLOCK
[3]
O
LASH
0
1
2
3
D
D
LE
370 family are designat-
C8
INPUT PIN
C9
Q
Q
[2]
O
Figure 7. Input/Clock Pins
Figure 6. input Pins
D
D
D
LE
Q
Q
Q
6
larity of the clock signal can also be controlled by the user.
Note that this polarity is separately controlled for input regis-
ters and output registers.
Timing Model
One of the most important features of the F
the simplicity of its timing. All delays are worst case and sys-
tem performance is unaffected by the features used or not
used on the parts. Figure 8 illustrates the true timing model for
the 8.5-ns devices. For combinatorial paths, any input to any
output incurs an 8.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input
set-up time to the output macrocells for any input is 5.0 ns and
the clock to output time is also 6.0 ns. Again, these measure-
ments are for any output and clock, regardless of the logic
used.
0
1
C12
0
1
2
3
C10 C11
Q
O
D
TO PIM
Q
TO CLOCK MUX ON
ALL INPUT MACROCELLS
C13, C14, C15
0
1
2
3
C10 C11
flash370-6
0
1
O
[4]
, OR C16
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
flash370–7
CPLD Family
TO PIM
F
[4]
LASH
LASH
TO CLOCK MUX
IN EACH
LOGIC BLOCK
370 family is
370™