CY7C374-100AC Cypress Semiconductor Corp, CY7C374-100AC Datasheet

CY7C374-100AC

Manufacturer Part Number

CY7C374-100AC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C374-100AC.pdf (7 pages)

Specifications of CY7C374-100AC

Family Name

FLASH370

# Macrocells

128

Propagation Delay Time

12ns

Number Of Logic Blocks/elements

# I/os (max)

In System Programmable

Mounting

Surface Mount

Pin Count

100

Package Type

TQFP

Memory Type

Flash

Lead Free Status / RoHS Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C374-100AC

Manufacturer:

CYP

Quantity:

200

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Features

Table 1. F

Cypress Semiconductor Corporation

• Flash erasable CMOS CPLDs

• High density

• Bus Hold capabilities on all I/Os and dedicated inputs

• High speed

• Fast Programmable Interconnect Matrix (PIM)

• Intelligent product term allocator

• Simple timing model

• Flexible clocking

• Security bit and user ID supported

• Packages

Device

— 32–128 macrocells

— 32–128 I/O pins

— Multiple clock pins

— t

— Uniform predictable delay, independent of routing

— 0–16 product terms to any macrocell

— Provides product term steering on an individual

— Provides product term sharing among local

— Doesn’t strand macrocells

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

— 2–4 clock pins per device

— Clock polarity control

— 44–160 pins

— PLCC, CLCC, PGA, and TQFP packages

371

372

373

374

375

basis

macrocells

= 5–7 ns

= 8.5–12 ns

= 6–7 ns

LASH

370 Selection Guide

Pins

160

Macrocells

128

Dedicated Inputs

•

3901 North First Street

UltraLogic™ High-Density Flash CPLDs

I/O Pins

General Description

The F

high-density programmable logic solutions with unparalleled

performance. Each member of the family is designed with Cy-

press’s state-of-the-art Flash technology. All of the devices are

electrically erasable and reprogrammable, simplifying product

inventory and reducing costs.

The F

of use and performance of the 22V10 to high-density CPLDs.

The architecture is based on a number of logic blocks that are

connected by a Programmable Interconnect Matrix (PIM).

Each logic block features its own product term array, product

term allocator array, and 16 macrocells. The PIM distributes

signals from one logic block to another as well as all inputs

from pins.

The family features a wide variety of densities and pin counts

to choose from. At each density there are two packaging op-

tions to choose from—one that is I/O intensive and another

that is register intensive. For example, the CY7C374 and

CY7C375 both feature 128 macrocells. On the CY7C374,

available in an 84-pin package, half of the macrocells are bur-

ied and half are available on I/O pins. On the CY7C375 all of

the macrocells are fed to I/O pins and the device is available

in the 160-pin package. Figure 1 shows a block diagram of the

CY7C374/5.

Functional Description

Programmable Interconnect Matrix

The Programmable Interconnect Matrix (PIM) consists of a

completely global routing matrix for signals from I/O pins and

feedbacks from the logic blocks. The PIM is an extremely ro-

bust interconnect that avoids fitting and density limitations.

Routing is automatically accomplished by software and the

propagation delay through the PIM is transparent to the user.

Signals from any pin or any logic block can be routed to any or

all logic blocks.

128

LASH

•

370™ family of CMOS CPLDs provides a range of

370 family is designed to bring the flexibility, ease

San Jose

Flip-Flops

140

•

CA 95134

Speed (t

8.5

CPLD Family

)

LASH

•

Speed (f

408-943-2600

July 20, 2000

143

125

100

370™

MAX

)

Related parts for CY7C374-100AC

CY7C374-100AC Summary of contents

Page 1

... At each density there are two packaging op- tions to choose from—one that is I/O intensive and another that is register intensive. For example, the CY7C374 and CY7C375 both feature 128 macrocells. On the CY7C374, available in an 84-pin package, half of the macrocells are bur- ied and half are available on I/O pins ...

Page 2

Logic Block Diagram 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I Functional Description (continued) The inputs to the PIM consist of all I/O and ...

Page 3

... PRODUCT TERM PIM ARRAY TO PIM Figure 2. Logic Block for CY7C371, CY7C373, and CY7C375 (I/O Intensive) FROM PIM PRODUCT TERM ARRAY TO PIM Figure 3. Logic Block for CY7C372 and CY7C374 (Register Intensive) 0–16 PRODUCT TERMS MACRO- CELL 6 0–16 PRODUCT MACRO- TERMS CELL 80 PRODUCT 0– ...

Page 4

Of the 86 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining six prod- uct terms in the logic block are output enable (OE) product terms. Each of the OE ...

Page 5

At the output of the macrocell, a polarity control mux is avail- able to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to oc- cur in many applications. The F 370 ...

Page 6

Dedicated/Clock Inputs Six pins on each member of the F 370 family are designat- LASH ed as input-only. There are two types of dedicated inputs on F 370 devices: input pins and input/clock pins. Figure 6 LASH illustrates the architecture ...

Page 7

... CUPL is a trademark of Logical Devices, Inc. © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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