CY7C374-100AC Cypress Semiconductor Corp, CY7C374-100AC Datasheet - Page 2

• Manufacturer Part Number: CY7C374-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C374-100AC

• Family Name: FLASH370
• # Macrocells: 128
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• In System Programmable: No
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pincount and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic block(s). Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also im-
proves the routing capacity of the F
An important feature of the PIM involves timing. The propaga-
tion delay through the PIM is accounted for in the timing spec-
ifications for each device. There is no additional delay for trav-
eling through the PIM. In fact, all inputs travel through the PIM.
Likewise, there are no route-dependent timing parameters on
the F
porated in all appropriate F
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp
automatically route designs for the F
of minutes. Finally, the rich routing resources of the F
family accommodate last minute logic changes while maintain-
ing fixed pin assignments.
Logic Block Diagram
LASH
370 devices. The worst-case PIM delays are incor-
I/O
I/O
I/O
I/O
16
32
48
0
™
–I/O
–I/O
–I/O
–I/O
and third-party development packages
15
31
47
63
16 I/Os
16 I/Os
16 I/Os
16 I/Os
LASH
(continued)
370 specifications.
LASH
LASH
370 family.
370 family in a matter
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
MACROCELLS
Figure 1. CY7C375 Block Diagram
64
C
D
A
B
INPUT
LASH
36
16
36
16
36
16
36
16
370
INPUTS
2
2
PIM
Logic Block
The logic block is the basic building block of the F
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used.
There are two types of logic blocks in the F
first type features an equal number (16) of I/O cells and mac-
rocells and is shown in Figure 2. This architecture is best for
I/O-intensive applications. The second type of logic block fea-
tures a buried macrocell along with each I/O macrocell. In oth-
er words, in each logic block, there are eight macrocells that
are connected to I/O cells and eight macrocells that are inter-
nally fed back to the PIM only. This organization is designed
for register-intensive applications and is displayed in Figure 3.
Note that at each F
I/O intensive and a register-intensive device is available.
Product Term Array
Each logic block features a 72 x 86 programmable product
term array. This array is fed with 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 86 product
terms in the array can be created from any of the 72 inputs.
CLOCK
INPUTS
INPUT/CLOCK
MACROCELLS
4
36
16
36
16
36
16
36
16
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
64
H
G
F
E
LASH
4
370 density (except the smallest), an
16 I/Os
16 I/Os
16 I/Os
16 I/Os
CPLD Family
I/O
I/O
I/O
I/O
LASH
F
112
96
80
64
LASH
–I/O
–I/O
–I/O
–I/O
370 family. The
111
95
79
127
370™
LASH
370