CY7C374-100AC Cypress Semiconductor Corp, CY7C374-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C374-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C374-100AC

• Family Name: FLASH370
• # Macrocells: 128
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• In System Programmable: No
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

FROM PTM
FROM PTM
At the output of the macrocell, a polarity control mux is avail-
able to select active LOW or active HIGH signals. This has the
added advantage of allowing significant logic reduction to oc-
cur in many applications.
The F
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Buried Macrocell
Some of the devices in the F
macrocells that do not feed individual I/O pins. Figure 5 dis-
plays the architecture of the I/O and buried macrocells for
these devices. The I/O macrocell is identical to the one on
devices without buried macrocells.
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combi-
natorial, a D flip-flop, a T flip-flop, or a latch. The clock for this
PRODUCT
PRODUCT
TERMS
TERMS
0–16
0–16
ASYNCHRONOUS
LASH
BLOCK RESET
ASYNCHRONOUS
370 macrocell features a feedback path to the PIM
BLOCK PRESET
4 SYSTEM CLOCKS (CY7C373–CY7C375)
2 SYSTEM CLOCKS (CY7C371–CY7C372)
LASH
0
1
2
3
0
1
2
3
370 family feature additional
C1 C0
C1
C0
[1]
Q
Q
[1]
0
1
Figure 5. I/O and Buried Macrocells
C7
Q
BURIED MACROCELL
I/O MACROCELL
D/T/L
D/T/L
P
R
P
R
Q
Q
FEEDBACK TO PIM
FEEDBACK TO PIM
FEEDBACK TO PIM
5
DECODE
register has the same options as described for the I/O macro-
cell. The primary difference between the I/O macrocell and the
buried macrocell is that the buried macrocell does not have the
ability to output data directly to an I/O pin.
One additional difference on the buried macrocell is the addi-
tion of input register capability. The buried macrocell can be
configured to act as an input register (D-type or latch) whose
input comes from the I/O pin associated with the neighboring
macrocell. The output of all buried macrocells is sent directly
to the PIM regardless of its configuration.
F
The I/O cell on the F
the I/O macrocell in Figures 4 and 5. The user can program
the I/O cell to change the way the three-state output buffer is
enabled and/or disabled. Each output can be set permanently
on (output only), permanently off (input only), or dynamically
controlled by one of two OE product terms.
DECODE
C2
C2
0
LASH
0
1
1
C3
C3
370 I/O Cell
Q
Q
0
1
LASH
C4
Q
370 devices is illustrated along with
2 BANK OE TERMS
“0”
“1”
0
1
2
3
CPLD Family
C5 C6
F
LASH
Q
I/O CELL
370™
flash370–5