CY7C374-100AC Cypress Semiconductor Corp, CY7C374-100AC Datasheet - Page 4

• Manufacturer Part Number: CY7C374-100AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C374-100AC

• Family Name: FLASH370
• # Macrocells: 128
• Propagation Delay Time: 12ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• In System Programmable: No
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Memory Type: Flash
• Lead Free Status / RoHS Status: Not Compliant

Of the 86 product terms, 80 are for general-purpose use for the
16 macrocells in the logic block. Four of the remaining six prod-
uct terms in the logic block are output enable (OE) product
terms. Each of the OE product terms controls up to eight of the
16 macrocells and is selectable on an individual macrocell ba-
sis. In other words, each I/O cell can select between one of two
OE product terms to control the output buffer. The first two of
these four OE product terms are available to the upper half of
the I/O macrocells in a logic block. The other two OE product
terms are available to the lower half of the I/O macrocells in a
logic block. The final two product terms in each logic block are
dedicated asynchronous set and asynchronous reset product
terms.
Product Term Allocator
Through the product term allocator, software automatically dis-
tributes product terms among the 16 macrocells in the logic
block as needed. A total of 80 product terms are available from
the local product term array. The product term allocator pro-
vides two important capabilities without affecting performance:
product term steering and product term sharing.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On F
uct terms are steered on an individual basis. Any number be-
tween 0 and 16 product terms can be steered to any macrocell.
Note that 0 product terms is useful in cases where a particular
macrocell is unused or used as an input register.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
Notes:
1.
PRODUCT
TERMS
0 16
C1 is not used on the CY7C371 and CY7C372.
ASYNCHRONOUS
BLOCK RESET
ASYNCHRONOUS
BLOCK PRESET
4 SYSTEM CLOCKS (CY7C373 - CY7C375)
2 SYSTEM CLOCKS (CY7C371 - CY7C372)
0
1
2
3
C0
S1 S0
C1
LASH
Q
[1]
370 devices, prod-
Figure 4. I/O Macrocell
I/O MACROCELL
D/T/L
R
P
Q
FEEDBACK TO PIM
FEEDBACK TO PIM
4
DECODE
one output has one or more product terms in its equation that
are common to other outputs, those product terms are only
programmed once. The F
lows sharing across groups of four output macrocells in a vari-
able fashion. The software automatically takes advantage of
this capability—the user does not have to intervene. Note that
greater usable density can often be achieved if the user “floats”
the pin assignment. This allows the compiler to group macro-
cells that have common product terms adjacently.
Note that neither product term sharing nor product term steer-
ing have any effect on the speed of the product. All worst-case
steering and sharing configurations have been incorporated in
the timing specifications for the F
F
I/O Macrocell
Within each logic block there are 8 or 16 I/O macrocells de-
pending on the device used. Figure 4 illustrates the architec-
ture of the I/O macrocell. The macrocell features a register that
can be configured as combinatorial, a D flip-flop, a T flip-flop,
or a level-triggered latch.
The register can be asynchronously set or asynchronously re-
set at the logic block level with the separate set and reset prod-
uct terms. Each of these product terms features programma-
ble polarity. This allows the registers to be set or reset based
on an AND expression or an OR expression.
Clocking of the register is very flexible. Depending on the de-
vice, either two or four global synchronous clocks are available
to clock the register. Furthermore, each clock features pro-
grammable polarity so that registers can be triggered on falling
as well as rising edges (see the Dedicated/Clock Inputs sec-
tion). Clock polarity is chosen at the logic block level.
C2
LASH
0
1
C3
370 Macrocell
Q
0
1
C4
Q
LASH
2 BANK OE TERMS
370 product term allocator al-
“0”
“1”
LASH
370 devices.
0
1
2
3
CPLD Family
C5 C6
F
LASH
Q
I/O CELL
370™
flash370–4