MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet - Page 77

• Manufacturer Part Number: MC9S08SH16CTL
• Manufacturer: Freescale

Specifications of MC9S08SH16CTL

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

1
2
6.3
The MC9S08SH32 Series devices contain a feature that allows for up to eight port pins to be tied together
externally to allow higher output current drive. The ganged output drive control register (GNGC) is a
write-once register that is used to enabled the ganged output feature and select which port pins will be used
as ganged outputs. The GNGEN bit in GNGC enables ganged output. The GNGPS[7:1] bits are used to
select which pin will be part of the ganged output.
When GNGEN is set, any pin that is enabled as a ganged output will be automatically configured as an
output and follow the data, drive strength and slew rate control of PTC0. The ganged output drive pin
mapping is shown in
Freescale Semiconductor
Drive Strength
Data Direction
Ganged output on PTC3-PTC0 not available on 16-pin packages, however PTC0 control registers are still used to control
ganged output.
When GNGEN = 1, PTC0 is forced to an output, regardless of the value in PTCDD0 in PTCDD.
Slew Rate
Port Pin
Control
Control
Control
Control
Data
Ganged Output
2
See the DC characteristics in the electrical section for maximum Port I/O
currents allowed for this MCU.
When a pin is enabled as ganged output, this feature will have priority over
any digital module. An enabled analog function will have priority over the
ganged output pin. See
GNGPS7
PTB5
Table
6-1.
Pin is automatically configured as output when pin is enabled as ganged output.
GNGPS6
PTB4
Table 6-1. Ganged Output Pin Enable
MC9S08SH32 Series Data Sheet, Rev. 2
Table 2-1
PTCDS0 in PTCDS controls drive strength of output
GNGPS5
PTCSE0 in PTCSE controls slew rate of output
PTB3
PTCD0 in PTCD controls data value of output
PRELIMINARY
for information on pin priority.
NOTE
GNGPS4
GNGC Register Bits
PTB2
GNGPS3
PTC3
GNGPS2
Chapter 6 Parallel Input/Output Control
PTC2
GNGPS1
PTC1
GNGEN
PTC0
1
77