MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet - Page 75
MC9S08SH16CTL
Manufacturer Part Number
MC9S08SH16CTL
Description
Manufacturer
Freescale
Datasheet
1.MC9S08SH16CTL.pdf
(328 pages)
Specifications of MC9S08SH16CTL
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
16KB
Lead Free Status / RoHS Status
Compliant
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Part Number
Manufacturer
Quantity
Price
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Part Number:
MC9S08SH16CTL
Manufacturer:
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Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08SH32 has three parallel I/O ports which include a total of 23 I/O pins and one output-only pin.
See
considerations of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
pin interrupts as shown in
functions so that when a peripheral is enabled, the I/O functions associated with the shared pins are
disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate disabled
PTxSEn = 0, low drive strength selected (PTxDSn = 0), and internal pull-ups disabled (PTxPEn = 0).
6.1
Reading and writing of parallel I/Os are performed through the port data registers. The direction, either
input or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled.
In general, whenever a pin is shared with both an alternate digital function and an analog function, the
analog function has priority such that if both the digital and analog functions are enabled, the analog
function controls the pin.
Freescale Semiconductor
Chapter 2, “Pins and
Port Data and Data Direction
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pull-up
devices or change the direction of unconnected pins to outputs so the pins
do not float.
Connections,” for more information about pin assignments and external hardware
Table
2-1. The peripheral modules have priority over the general-purpose I/O
MC9S08SH32 Series Data Sheet, Rev. 2
PRELIMINARY
NOTE
Figure
6-1.
75
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