MC9S08SH16CTL Freescale, MC9S08SH16CTL Datasheet - Page 28

• Manufacturer Part Number: MC9S08SH16CTL
• Manufacturer: Freescale

Specifications of MC9S08SH16CTL

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 2 Pins and Connections
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5
The MC9S08SH32 Series series of MCUs support up to 23 general-purpose I/O pins and 1 output-only
pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, etc.).
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pull-up device. Immediately after reset, all of these pins are configured as high-impedance general-purpose
inputs with internal pull-up devices disabled.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see
The MC9S08SH32 Series devices contain a ganged output drive feature that allows a safe and reliable
method of allowing pins to be tied together externally to produce a higher output current drive. See
6.3, “Ganged
28
Chapter 6, “Parallel Input/Output
General-Purpose I/O and Peripheral Ports
Output” for more information for configuring the port pins for ganged output drive.
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip pull-up
devices or change the direction of unused pins to outputs so they do not float.
When using the 20-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded PTC7-PTC4 and
PTA7-PTA6 pins to outputs so the pins do not float.
When using the 16-pin devices, the user must either enable on-chip pullup
devices or change the direction of non-bonded out PTC7-PTC0 and
PTA7-PTA6 pins to outputs so the pins do not float.
MC9S08SH32 Series Data Sheet, Rev. 2
Control.”
PRELIMINARY
NOTE
Freescale Semiconductor
Section