LSI53CF92A LSI, LSI53CF92A Datasheet - Page 93

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Chapter 5
Command Set
All LSI53CF92A instructions may be issued in two forms: DMA and
non-DMA. DMA commands move data between memory and the SCSI
bus, while non-DMA commands move data between the FIFO and the
SCSI bus. Non-DMA commands require the microprocessor to move
data between the FIFO and memory. DMA commands require an
external DMA controller to move data between the FIFO and memory. A
command that is issued to the
Command register set is a DMA command. A command that is issued
with bit 7 not set is a non-DMA command. DMA commands load the
transfer counter with the value in the
Transfer Counter
issued. The word “sequence” in the command name indicates that the
Sequence Step
the
command completed normally or to aid in data recovery if the command
did not complete normally.
This chapter contains the following sections:
Table 5.1
LSI53CF92A Fast SCSI Controller
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Sequence Step
Section 5.1, “Illegal Commands”
Section 5.2, “Miscellaneous Command Group”
Section 5.3, “Disconnected State Command Group”
Section 5.4, “Initiator Command Group”
Section 5.5, “Target Command Group”
lists the Command Set.
register is affected by executing the command. Check
register must be loaded before any DMA command is
register after using these commands to verify the
Command
Transfer Counter
register with bit 7 of the
register, so the
5-1