LSI53CF92A LSI, LSI53CF92A Datasheet - Page 134

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

Table 6.15
1. Alternate DMA is disabled.
2. DREQ may stay HIGH if the FIFO has room to accept another byte during DMA write, or send
3. DACK/ must toggle once for each access.
4. DBRD/ trailing edge may precede or follow DACK/ trailing edge. The recommended value is:
5. DBWR/ trailing edge may precede or follow DACK/ trailing edge. The recommended value is:
6-18
Symbol
another byte during DMA read. If the current DMA acknowledge cycle fills the FIFO (write) or
empties the FIFO (read), then DREQ goes LOW.
t
maximum, and the time from DACK/ HIGH to data bus disable is 2 ns minimum and 25 ns maximum.
t
DACK/ HIGH is 10 ns minimum.
9
14
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
0. If DBRD/ is held LOW past DACK/, the time from DACK/ LOW to stable data is 30 ns
0. If DBWR/ is past DACK/, the data setup to DACK/ HIGH is 10 ns minimum; data hold from
Parameter
DACK/ LOW to DREQ LOW
DACK/ HIGH to DREQ HIGH
DACK/ HIGH to DACK/ LOW
DACK/ pulse width
DACK/ period (LOW to LOW)
DACK/ period (HIGH to HIGH)
DACK/ LOW to DBRD/ LOW
DBRD/ pulse width
DBRD/ HIGH to DACK/ HIGH
DBRD/ to data valid
DBRD/ HIGH to data bus disable
DACK/ LOW to DBWR/ LOW
DBWR/ pulse width
DBWR/ HIGH to DACK/ HIGH
Data setup to DBWR/ HIGH
Data hold from DBWR/ HIGH
DBWR/ HIGH to DBWR/ LOW
DMA Interface (Multiplexed Mode Only)
Table 6.15
Electrical Specifications
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the DMA Interface, Multiplexed Mode only.
t
t
CP
CP
3 t
3 t
Min
30
30
30
15
30
–
0
0
0
2
0
0
4
CP
CP
+5
+5
1
Max
30
30
30
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
–
–
–
–
–
–
–
–
–
–
2
2
3
4
4
5
5