LSI53CF92A LSI, LSI53CF92A Datasheet - Page 72

• Manufacturer Part Number: LSI53CF92A
• Manufacturer: LSI

Specifications of LSI53CF92A

• Lead Free Status / RoHS Status: Not Compliant

4-22
Table 4.5
Bits 5 and 4 control when REQ/ or ACK/ asserts by selecting one
of four input clock edges. Assertion of the REQ/ and ACK/ signals is
not dependent on the FASTCLK bit. The assertion delay is shown
in
Table 4.6
The least significant four bits of this register specify whether the FSC
transfers data phase bytes synchronously or asynchronously. Zero
specifies asynchronous transfer. Any other value specifies the
synchronous offset, the number of data phase bytes that may be sent
synchronously without an acknowledge (either REQ/ or ACK/),
depending on whether the FSC is in initiator or target mode.
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
FASTCLK
Synchronous Offset
Table
Register Bits [5:4]
Status
1
1
1
1
0
0
0
0
4.6.
00
01
10
11
REQ/ ACK/ Deassertion Delay Selection
REQ/ ACK/ Assertion Delay Selection
Offset Register
Synchronous
Bits [7:6]
00
01
10
11
00
01
10
11
(In Input Clock Cycles)
Assertion Delay
1 1/2 Clocks
REQ/ ACK/
0 (Default)
1/2 Clock
1 Clock
REQ/ ACK/
Deassertion Delay
(Input Clock Cycles)
No Delay (Default)
1/2 Clock
1 Clock
1 1/2 Clocks
No Delay
1/2 Clock Early
1 Clock
1/2 Clock