PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 9

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD device. A blank device can be completely
programmed. The JTAG signals (TMS, TCK,
TSTAT, TERR, TDI, TDO) can be multiplexed with
other functions on Port C. Table 2 indicates the
JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire PSD
device can be programmed or erased without the
use of the MCU. The primary Flash memory can
also be programmed in-system by the MCU
executing the programming algorithms out of the
secondary memory, or SRAM. The secondary
memory can be programmed the same way by
executing out of the primary Flash memory. The
PLD or other PSD Configuration blocks can be
programmed through the JTAG port or a device
programmer. Table 3 indicates which
programming methods can program different
functional blocks of the PSD.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
Table 3. Methods of Programming Different Functional Blocks of the PSD
Primary Flash Memory
Secondary Flash Memory
PLD Array (DPLD and CPLD)
PSD Configuration
Functional Block
Yes
Yes
Yes
Yes
JTAG Programming
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD also has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled “POWER MANAGEMENT” on page
56 for more details.
Table 2. JTAG SIgnals on Port C
PC0
PC1
PC3
PC4
PC5
PC6
Port C Pins
Yes
Yes
Yes
Yes
Device Programmer
TMS
TCK
TSTAT
TERR
TDI
TDO
JTAG Signal
Yes
Yes
No
No
PSD834F2V
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