PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet

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Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM FEATURES SUMMARY ■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUs ■ 3.3 V±10% SINGLE SUPPLY VOLTAGE ■ 2 MBIT OF PRIMARY FLASH MEMORY (8 UNIFORM SECTORS, 32K ...

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PSD834F2V TABLE OF CONTENTS SUMMARY DESCRIPTION ...

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PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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PSD834F2V RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SUMMARY DESCRIPTION The PSD family of memory systems for microcon- trollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for em- bedded designs. PSD devices combine many of the peripheral ...

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PSD834F2V KEY FEATURES ■ A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a READ or WRITE ...

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Figure 2. PSD Block Diagram PSD834F2V AI05793b 7/95 ...

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PSD834F2V PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 2 shows the architecture of the PSD device family. The functions of each block are de- scribed briefly in the following sections. Many of the blocks perform multiple ...

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JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows complete programming of the entire PSD device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, ...

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PSD834F2V DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft Express, a Windows-based software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language ...

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PIN DESCRIPTION Table 4 describes the signal names and signal functions of the PSD. Table 4. Pin Description (for the PLCC52 package - Note 1) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or ...

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PSD834F2V Pin Name Pin Type These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O – write to or read from a standard output or input port. PA0 29 2. ...

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Pin Name Pin Type PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read from a standard output or input port. 2. CPLD macrocell (McellBC5) output. ...

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PSD834F2V Table 5. I/O Port Latched Address Output Assignments (Note 1) MCU 8051XA (8-bit) N/A 80C251 (page mode) N/A All other 8-bit multiplexed Address a3-a0 8-bit non-multiplexed bus N/A Note: 1. See the section entitled “I/O PORTS”, on page 46, ...

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DETAILED OPERATION As shown in Figure 2, the PSD consists of six ma- jor types of functional blocks: ■ Memory Blocks ■ PLD Blocks MCU Bus Interface ■ ■ I/O Ports ■ Power Management Unit (PMU) ■ JTAG Interface The ...

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PSD834F2V Table 7. Instructions FS0-FS7 or Instruction CSBOOT0- Cycle 1 CSBOOT3 “Read” READ Read Main AAh X555h Flash ID Read Sector AAh@ 1 6,8,13 X555h Protection Program a AAh X555h Flash ...

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INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially de- coded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly ...

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PSD834F2V Reading the Erase/Program Status Bits. The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Pro- gram cycle of Flash memory. These status bits minimize the time that the ...

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Programming Flash Memory Flash memory must be erased prior to being pro- grammed. A byte of Flash memory is erased to all 1s (FFh), and is programmed by setting selected bits to '0.' The MCU may erase Flash memory all ...

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PSD834F2V Data Toggle. Checking the Toggle Flag (DQ6) Bit is a method of determining whether a Program or Erase cycle is in progress or has completed. Figure 5 shows the Data Toggle algorithm. When the MCU issues a Program instruction, ...

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Erasing Flash Memory Flash Bulk Erase. The Flash Bulk Erase instruc- tion uses six WRITE operations followed by a READ operation of the status register, as de- scribed in Table 7. If any byte of the Bulk Erase in- struction ...

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PSD834F2V Specific Features Flash Memory Sector Protect. Each and secondary Flash memory sector can be sepa- rately protected against Program and Erase cy- cles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode ...

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SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express Configuration. Sector Select and ...

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PSD834F2V Memory Select Configuration for MCUs with Separate Program and Data Spaces. The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and 80C51XA, have separate address spaces for Program memory (selected using Program Select Enable (PSEN, ...

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Combined Space Modes. The Data spaces are combined into one memory space that allows the primary Flash memory, sec- ondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN, CNTL2) Figure 8. 8031 Memory Modules – ...

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PSD834F2V Page Register The 8-bit Page Register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0- ...

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PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: ...

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PSD834F2V Figure 10. PLD Diagram 8 PAGE ATA REGISTER US DECODE PLD 73 OUTPUT MACROCELL FEEDBACK 16 CPLD 73 DIRECT MACROCELL INPUT TO MCU DATA BUS INPUT MACROCELL & INPUT PORTS 24 3 PORT D INPUTS 28/95 8 PRIMARY FLASH ...

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Decode PLD (DPLD) The DPLD, shown in Figure 11, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: ■ 8 Sector Select (FS0-FS7) signals for ...

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PSD834F2V Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three ...

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Figure 12. Macrocell and I/O Port BUS INPUT PLD MUX MUX ARRAY AND BUS INPUT PLD PSD834F2V MUX MUX 31/95 ...

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PSD834F2V Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as ...

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Product Term Allocator The CPLD has a Product Term Allocator. The PS- Dabel compiler uses the Product Term Allocator to borrow and place product terms from one macro- cell to another. The following list summarizes how product terms are allocated: ...

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PSD834F2V Figure 13. CPLD Output Macrocell 34/95 ARRAY AND BUS INPUT PLD ...

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The OMC Mask Register. There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Out- put Macrocells (OMC). The default ...

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PSD834F2V Figure 14. Input Macrocell 36/95 ARRAY AND BUS INPUT PLD ...

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Figure 15. Handshaking Communication Using Input Macrocells PSD834F2V 37/95 ...

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PSD834F2V MCU BUS INTERFACE The “no-glue logic” MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Key 8-bit MCUs, with their bus types and control signals, are shown in Table 14. The interface ...

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Figure 16. An Example of a Typical 8-bit Multiplexed Bus Interface MCU WR RD BHE ALE RESET PSD 15:8 ] PSD834F2V PORT A ( OPTIONAL ) ADIO PORT A ...

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PSD834F2V PSD Interface to a Non-Multiplexed 8-bit Bus. Figure 17 shows an example of a system using a MCU with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO Port, and the data bus ...

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MCU Bus Interface Examples Figure 18 to Figure 21 show examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The ...

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PSD834F2V The first configuration is 80C31 compatible, and the bus interface to the PSD is identical to that shown in Figure 18. The second and third configu- rations have the same bus connection as shown in Figure 17. There is ...

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Figure 19. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 P3.2/INT0 ...

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PSD834F2V 80C51XA. The Philips 80C51XA MCU family sup- ports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multi- plexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit ...

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Figure 21 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit mul- tiplexed mode with E and R/W settings. The DPLD Figure 21. Interfacing the PSD with a 68HC11 68HC11 ...

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PSD834F2V I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions ...

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The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the ...

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PSD834F2V Table 18. Port Operating Modes Port Mode MCU I/O Yes PLD I/O McellAB Outputs Yes McellBC Outputs No Additional Ext. CS Outputs No PLD Inputs Yes Address Out Yes (A7 – 0) Address In Yes Data Port Yes (D7 ...

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Table 20. I/O Port Latched Address Output Assignments MCU Port A (PA3-PA0) 1 8051XA (8-bit) N/A 80C251 N/A (Page Mode) All Other Address a3-a0 8-bit Multiplexed 8-bit N/A Non-Multiplexed Bus Note: 1. N/A = Not Applicable. Address In Mode For ...

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PSD834F2V Port Configuration Registers (PCR) Each Port has a set of Port Configuration Regis- ters (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in ...

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Table 25. Drive Register Pin Assignment Drive Bit 7 Bit 6 Register Open Open Port A Drain Drain Open Open Port B Drain Drain Open Open Port C Drain Drain 1 1 Port Note ...

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PSD834F2V Ports A and B – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure 24. The two ports can be configured to perform one or more of the following functions: ■ ...

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Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 25): ■ MCU I/O Mode ■ CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or ...

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PSD834F2V Port D – Functionality and Structure Port D has three I/O pins. See Figure 26 and Fig- ure 27. This port does not support Address Out mode, and therefore no Control Register is re- quired. Port D can be ...

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External Chip Select The CPLD also provides three External Chip Se- lect (ECS0-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS0-ECS2) consists of one product Figure 27. Port D External ...

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PSD834F2V POWER MANAGEMENT All PSD devices offer configurable power saving options. These options may be used individually or in combinations, as follows: ■ All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with power ...

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Automatic Power-down (APD) Unit and Power- down Mode. The APD Unit, shown in Figure 28, puts the PSD into Power-down mode by monitor- ing the activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as ...

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PSD834F2V For Users of the HC11 (or compatible). The HC11 turns off its E clock when it sleeps. There- fore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power-down mode, you ...

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PLD Power Management The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By setting the bit to '1,' the Turbo mode is off and the PLDs con- sume the specified standby current ...

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PSD834F2V PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal Flash memory, EEPROM, SRAM, and I/O blocks ...

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RESET TIMING AND DEVICE STATUS AT RESET Upon Power-up, the PSD requires a Reset (RE- SET) pulse of duration t NLNH-PO steady. During this period, the device loads inter- nal configurations, clears some of the registers and sets the Flash ...

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PSD834F2V Table 32. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 and ...

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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface block can be enabled on Port C (see Table 33). All memory blocks (pri- mary and secondary Flash memory), PLD logic, and PSD Configuration Register bits may be pro- ...

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PSD834F2V JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status ...

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AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD: ❏ DC Electrical Specification ❏ AC Timing Specification PLD Timing ■ – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing ■ ...

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PSD834F2V Table 35. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode ...

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Table 36. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number ...

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... Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω) 68/95 plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 1 or Hi-Z) ...

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DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed ...

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PSD834F2V Table 41. AC Symbols for PLD Timing Signal Letters A Address Input C CEout Output D Input Data E E Input G Internal WDOG_ON signal I Interrupt Input L ALE Input N Reset Input or Output P Port Signal ...

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Table 42. DC Characteristics Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis HYS V (min) for ...

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PSD834F2V Figure 35. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 43. CPLD Combinatorial Timing Symbol Parameter CPLD Input Pin/ t Feedback to CPLD PD Combinatorial Output CPLD Input to CPLD t EA Output Enable CPLD ...

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Figure 36. Synchronous Clock Mode Timing – PLD CLKIN INPUT REGISTERED OUTPUT Table 44. CPLD Macrocell Synchronous Clock Mode Timing Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f ) CNT Maximum Frequency Pipelined Data t ...

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PSD834F2V Figure 37. Asynchronous Reset / Preset RESET/PRESET INPUT REGISTER OUTPUT Figure 38. Asynchronous Clock Mode Timing (product term clock) CLOCK INPUT REGISTERED OUTPUT 74/95 tARPW tARP tCHA tCLA tSA tHA tCOA AI02864 AI02859 ...

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Table 45. CPLD Macrocell Asynchronous Clock Mode Timing Symbol Parameter Conditions Maximum Frequency 1/(t External Feedback Maximum Frequency f MAXA Internal 1/(t SA Feedback (f ) CNTA Maximum 1/(t Frequency Pipelined Data Input Setup t SA Time t Input Hold ...

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PSD834F2V Figure 39. Input Macrocell Timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 46. Input Macrocell Timing Symbol Parameter t Input Setup Time IS t Input Hold Time IH t NIB Input High Time INH t NIB Input ...

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Figure 40. READ Timing ALE/ MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS) E R/W t AVPV Note and t are not required for 80C251 in Page Mode or 80C51XA in Burst ...

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PSD834F2V Table 47. READ Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to ...

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Figure 41. WRITE Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ...

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PSD834F2V Table 48. WRITE Timing Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of ...

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Table 49. Program, WRITE and Erase Times Symbol Flash Program 1 Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles (per Sector) ...

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PSD834F2V Figure 42. Peripheral I/O READ Timing ALE/ BUS CSI RD Table 50. Port A Peripheral Data Mode READ Timing Symbol Parameter t Address Valid to Data Valid AVQV–PA t CSI Valid to Data Valid SLQV– ...

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Figure 43. Peripheral I/O WRITE Timing ALE / BUS WR Table 51. Port A Peripheral Data Mode WRITE Timing Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV–PA ...

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PSD834F2V Figure 44. Reset (RESET) Timing V (min NLNH-PO Power-On Reset RESET Table 52. Reset (Reset) Timing Symbol Parameter t RESET Active Low Time NLNH t Power On Reset Active Low Time NLNH– Warm ...

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Figure 45. ISC Timing t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 54. ISC Timing Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low ...

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PSD834F2V PACKAGE MECHANICAL In order to meet environmental requirements, ST offers these devices in different grades of ECO- PACK® packages, depending on their level of en- vironmental compliance. Figure 46. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 ...

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Figure 47. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 PSD834F2V AD15 46 AD14 45 44 AD13 AD12 43 ...

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PSD834F2V Figure 48. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. 88/ ...

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Table 55. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions Symb. Typ 2. 13.20 D1 10.00 D2 7.80 E 13.20 E1 10.00 E2 7.80 e 0.65 L 0.88 L1 1.60 α ...

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PSD834F2V Figure 49. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 56. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ. A ...

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PART NUMBERING Table 57. Ordering Information Scheme Example: Device Type PSD8 = 8-bit PSD with register logic PSD9 = 8-bit PSD with combinatorial logic SRAM Capacity Kbit Flash Memory Capacity Mbit (256K x 8) ...

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PSD834F2V APPENDIX A. PQFQ52 PIN ASSIGNMENTS Table 58. PQFP52 Connections (Figure 46) Pin Number Pin Assignments ...

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APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 59. PLCC52 Connections Pin Number Pin Assignments Pin ...

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PSD834F2V REVISION HISTORY Table 60. Document Revision History Date Version 15-Feb-2002 1.0 Document written 18-Nov-03 2.0 Reformatted; correct package references (Figure 1) Updated datasheet status to “not for new design”. Backup battery feature removed: updated FEATURES SUMMARY, Table 4 (pins ...

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