PSD834F2V10MI STMicroelectronics, PSD834F2V10MI Datasheet - Page 6

• Manufacturer Part Number: PSD834F2V10MI
• Manufacturer: STMicroelectronics

Specifications of PSD834F2V10MI

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: PQFP
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Compliant

PSD834F2V
KEY FEATURES
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A simple interface to 8-bit microcontrollers that
use either multiplexed or non-multiplexed
busses. The bus interface logic uses the control
signals generated by the microcontroller
automatically when the address is decoded and
a READ or WRITE is performed. A partial list of
the MCU families supported include:
– Intel 8031, 80196, 80186, 80C251, and
– Motorola 68HC11, 68HC16, 68HC12, and
– Philips 8031 and 8051XA
– Zilog Z80 and Z8
Internal 2 Mbit Flash memory. This is the main
Flash memory. It is divided into 8 equal-sized
blocks that can be accessed with user-specified
addresses.
Internal secondary 256 Kbit Flash boot memory.
It is divided into 4 equal-sized blocks that can be
accessed with user-specified addresses. This
secondary memory brings the ability to execute
code and update the main Flash concurrently.
Internal 64 Kbit SRAM.
CPLD with 16 Output macrocells (OMCs) and
24 Input macrocells (IMCs). The CPLD may be
used to efficiently implement a variety of logic
functions for internal and external control.
Examples include state machines, loadable
shift registers, and loadable counters.
Decode PLD (DPLD) that decodes address for
selection of internal memory blocks.
80386EX
683XX
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27 individually configurable I/O port pins that
can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– 16 of the I/O ports may be configured as
Standby current as low as 25µA.
Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
Internal page register that can be used to
expand the microcontroller address space by a
factor of 256.
Internal programmable Power Management
Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can
automatically detect a lack of microcontroller
activity and put the PSD into Power-down
mode.
Erase/WRITE cycles:
– Flash memory – 100,000 minimum
– PLD – 1,000 minimum
– Data Retention: 15 year minimum (for Main
open-drain outputs.
Flash memory, Boot, PLD and Configuration
bits)