ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 68

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 42.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hc PInterrupt register: bit allocation
10.4.4 Hc PInterrupt register (R/W: 24H/A4H)
reserved
R/W
15
7
0
All the bits in this register will be active on power-on reset. However, none of the active
bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the respective
bits in the Hc PInterruptEnable register, and together with bit 0 of the
HcHardwareConfiguration register.
After this register (24H for read) is read, the bits that are active will not be reset, until
logic 1 is written to the bits in this register (A4H for write) to clear it. To clear all the
enabled bits in this register, the HCD must write FFH to this register.
Code (Hex): 24 — read
Code (Hex): A4 — write
Table 43.
Bit
15 to 7
6
5
4
3
2
ClkReady
R/W
14
6
0
Hc PInterrupt register: bit description
Symbol
-
ClkReady
HC
Suspended
OPR_Reg
-
AllEOT
Interrupt
Suspended
R/W
HC
13
5
0
Rev. 04 — 29 January 2009
Description
reserved
0 — no event
1 — clock is ready. After a wake-up is sent, there is a wait for clock
ready. (Maximum is 1 ms, and typical is 160 s)
0 — no event
1 — the HC has been suspended and no USB activity is sent from the
microprocessor for each ms. When the microprocessor wants to
suspend the HC, the microprocessor must write to the HcControl
register. And when all downstream devices are suspended, then
the HC stops sending SOF; the HC is suspended by having the
HcControl register written into.
0 — no event
1 — There are interrupts from HC side. Need to read HcControl and
HcInterrupt registers to detect type of interrupt on the HC (if the HC
requires the Operational register to be updated)
reserved
0 — no event
1 — implies that data transfer has been completed via PIO transfer or
DMA transfer. Occurrence of internal or external EOT will set this bit.
OPR_Reg
R/W
12
4
0
reserved
R/W
00H
reserved
USB single-chip host and device controller
R/W
11
3
0
Interrupt
AllEOT
R/W
10
2
0
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
ATLInt
R/W
9
1
0
SOFITLInt
R/W
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8
0
0