ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 135

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. HcControl register: bit allocation . . . . . . . . . . .46
Table 11. HcControl register: bit description . . . . . . . . . .46
Table 12. HcCommandStatus register: bit allocation . . . .47
Table 13. HcCommandStatus register: bit description . . .48
Table 14. HcInterruptStatus register: bit allocation . . . . .48
Table 15. HcInterruptStatus register: bit description . . . .49
Table 16. HcInterruptEnable register: bit allocation . . . . .50
Table 17. HcInterruptEnable register: bit description . . . .50
Table 18. HcInterruptDisable register: bit allocation . . . .51
Table 19. HcInterruptDisable register: bit description . . .51
Table 20. HcFmInterval register: bit allocation . . . . . . . .52
Table 21. HcFmInterval register: bit description . . . . . . .52
Table 22. HcFmRemaining register: bit allocation . . . . . .53
Table 23. HcFmRemaining register: bit description . . . . .53
Table 24. HCFmNumber register: bit allocation . . . . . . . .54
Table 25. HcFmNumber register: bit description . . . . . . .54
Table 26. HcLSThreshold register: bit allocation . . . . . . .54
Table 27. HcLSThreshold register: bit description . . . . . .55
Table 28. HcRhDescriptorA register: bit description . . . .56
Table 29. HcRhDescriptorA register: bit description . . . .57
Table 30. HcRhDescriptorB register: bit allocation . . . . .58
Table 31. HcRhDescriptorB register: bit description . . . .58
Table 32. HcRhStatus register: bit allocation . . . . . . . . . .59
Table 33. HcRhStatus register: bit description . . . . . . . . .59
Table 34. HcRhPortStatus[1:2] register: bit allocation . . .60
Table 35. HcRhPortStatus[1:2] register: bit description . .61
Table 36. HcHardwareConfiguration register: bit
Table 37. HcHardwareConfiguration register: bit
Table 38. HcDMAConfiguration register: bit allocation . .65
Table 39. HcDMAConfiguration register: bit description .65
Table 40. HcTransferCounter register: bit allocation . . . .66
Table 41. HcTransferCounter register: bit description . . .66
Table 42. HcmPInterrupt register: bit allocation . . . . . . . .67
Table 43. HcmPInterrupt register: bit description . . . . . .67
Table 44. HcmPInterruptEnable register: bit allocation . .68
ISP1161A1_4
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description for LQFP64 . . . . . . . . . . . . . . . .7
I/O port addressing . . . . . . . . . . . . . . . . . . . . .13
Proprietary Transfer Descriptor (PTD): bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Proprietary Transfer Descriptor (PTD): bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Run results of the C program example . . . . . .35
HC Control register summary . . . . . . . . . . . . .44
HcRevision register: bit allocation . . . . . . . . . .45
HcRevision register: bit description . . . . . . . . .45
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Rev. 04 — 29 January 2009
Table 45. HcmPInterruptEnable register: bit description 68
Table 46. HcChipID register: bit allocation . . . . . . . . . . . 69
Table 47. HcChipID register: bit description . . . . . . . . . . 69
Table 48. HcScratch register: bit allocation . . . . . . . . . . 70
Table 49. HcScratch register: bit description . . . . . . . . . 70
Table 50. HcSoftwareReset register: bit allocation . . . . . 70
Table 51. HcSoftwareReset register: bit description . . . . 70
Table 52. HcITLBufferLength register: bit allocation . . . . 71
Table 53. HcITLBufferLength register: bit description . . . 71
Table 54. HcATLBufferLength register: bit allocation . . . 71
Table 55. HcATLBufferLength register: bit description . . 72
Table 56. HcBufferStatus register: bit allocation . . . . . . . 72
Table 57. HcBufferStatus register: bit description . . . . . . 72
Table 58. HcReadBackITL0Length register: bit
Table 59. HcReadBackITL0Length register: bit
Table 60. HcReadBackITL1Length register: bit
Table 61. HcReadBackITL1Length register: bit
Table 62. HcITLBufferPort register: bit allocation . . . . . . 74
Table 63. HcITLBufferPort register: bit description . . . . . 74
Table 64. HcATLBufferPort register: bit allocation . . . . . 74
Table 65. HcATLBufferPort register: bit description . . . . 75
Table 66. Endpoint access and programmability . . . . . . 78
Table 67. Programmable FIFO size . . . . . . . . . . . . . . . . 79
Table 68. Memory configuration example . . . . . . . . . . . . 79
Table 69. Summary of control bits . . . . . . . . . . . . . . . . . 83
Table 70. Endpoint selection for DMA transfer . . . . . . . . 84
Table 71. 8237 compatible mode: pin functions . . . . . . . 85
Table 72. DACK-only mode: pin functions . . . . . . . . . . . 86
Table 73. Summary of EOT conditions for a bulk
Table 74. Recommended EOT usage for isochronous
Table 75. DC command and register summary . . . . . . . 89
Table 76. DcEndpointConfiguration register: bit
Table 77. DcEndpointConfiguration register: bit
Table 78. DcAddress register: bit allocation . . . . . . . . . . 92
Table 79. DcAddress register: bit description . . . . . . . . . 92
Table 80. DcMode register: bit allocation . . . . . . . . . . . . 93
Table 81. DcMode register: bit description . . . . . . . . . . . 93
Table 82. DcHardwareConfiguration register: bit
Table 83. DcHardwareConfiguration register: bit
USB single-chip host and device controller
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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