ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 136

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 84. DcInterruptEnable register: bit allocation . . . . .96
Table 85. DcInterruptEnable register: bit description . . . .96
Table 86. DcDMAConfiguration register: bit allocation . .97
Table 87. DcDMAConfiguration register: bit description .97
Table 88. DcDMACounter register: bit allocation . . . . . . .98
Table 89. DcDMACounter register: bit description . . . . .98
Table 90. Endpoint FIFO organization . . . . . . . . . . . . . . .99
Table 91. Example of endpoint FIFO access . . . . . . . . . .99
Table 92. DcEndpointStatus register: bit allocation . . . .100
Table 93. DcEndpointStatus register: bit description . .100
Table 94. DcEndpointStatusImage register: bit
Table 95. DcEndpointStatusImage register: bit
Table 96. DcErrorCode register: bit allocation . . . . . . . .102
Table 97. DcErrorCode register: bit description . . . . . .102
Table 98. Transaction error codes . . . . . . . . . . . . . . . . .103
Table 99. Lock register: bit allocation . . . . . . . . . . . . . .103
Table 100. Lock register: bit description . . . . . . . . . . . . .104
Table 101.DcScratch register: bit allocation . . . . . . . . . .104
Table 102.DcScratch register: bit description . . . . . . . . .104
Table 103.DcFrameNumber register: bit allocation . . . .105
Table 104.DcFrameNumber register: bits description . .105
Table 105.Example of DcFrameNumber register
Table 106.DcChipID register: bit allocation . . . . . . . . . .105
Table 107.DcChipID register: bit description . . . . . . . . .106
Table 108.DcInterrupt register: bit allocation . . . . . . . . .106
Table 109. DcInterrupt register: bit description . . . . . . . .106
Table 110. Absolute maximum ratings . . . . . . . . . . . . . . 112
Table 111. Recommended operating conditions . . . . . . . 112
Table 112. Static characteristics; supply pins . . . . . . . . . 113
Table 113. Static characteristics: digital pins . . . . . . . . . . 113
Table 114. Static characteristics: analog I/O pins
Table 115. Dynamic characteristics . . . . . . . . . . . . . . . . . 115
Table 116. Dynamic characteristics: analog I/O pins
Table 117. Dynamic characteristics: HC Programmed
Table 118. Dynamic characteristics: DC Programmed
Table 119. Dynamic characteristics: HC single-cycle DMA
Table 120.Dynamic characteristics: HC burst mode DMA
Table 121.Dynamic characteristics: DC single-cycle DMA
Table 122.Dynamic characteristics: DC single-cycle DMA
Table 123.Dynamic characteristics: DC single-cycle DMA
Table 124.Dynamic characteristics: EOT timing in
Table 125.Dynamic characteristics: DC burst mode DMA
Table 126.Dynamic characteristics: EOT timing in DC burst
ISP1161A1_4
Product data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
description . . . . . . . . . . . . . . . . . . . . . . . . . . .101
access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
(D+, D ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
(D+, D ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
interface timing . . . . . . . . . . . . . . . . . . . . . . . 116
interface timing . . . . . . . . . . . . . . . . . . . . . . . 117
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
timing (8237 mode) . . . . . . . . . . . . . . . . . . . .121
read timing in DACK-only mode . . . . . . . . . .121
write timing in DACK-only mode . . . . . . . . . .122
DC single-cycle DMA . . . . . . . . . . . . . . . . . . .123
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Rev. 04 — 29 January 2009
Table 127.SnPb eutectic process (from J-STD-020C) . . 132
Table 128.Lead-free process (from J-STD-020C) . . . . . 132
Table 129.Revision history . . . . . . . . . . . . . . . . . . . . . . . 133
USB single-chip host and device controller
mode DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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