ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 13

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

8. Microprocessor bus interface
ISP1161A1_4
Product data sheet
7.6 GoodLink
8.1 Programmed I/O (PIO) addressing mode
8.2 DMA mode
Indication of a good USB connection is provided at pin GL through GoodLink technology.
During enumeration, the LED indicator will blink on momentarily. When the DC has been
successfully enumerated (the device address is set), the LED indicator will remain
permanently on. Upon each successful packet transfer (with ACK) to and from the
ISP1161A1 the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain
off.
This feature provides a user-friendly indication of the status of the USB device, the
connected hub and the USB traffic. It is a useful field diagnostics tool for isolating faulty
equipment. It can therefore help to reduce field support and hotline overhead.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1161A1 appears as a
memory device with a 16-bit data bus and uses only two address lines: A1 and A0 to
access the internal control registers and FIFO buffer RAM. Therefore, the ISP1161A1
occupies only four I/O ports or four memory locations of a microprocessor. External
microprocessors can read from or write to the ISP1161A1 internal control registers and
FIFO buffer RAM through the Programmed I/O (PIO) operating mode.
Programmed I/O interface between a microprocessor and an ISP1161A1.
The ISP1161A1 also provides DMA mode for external microprocessors to access its
internal FIFO buffer RAM. Data can be transferred by DMA operation between a
microprocessor’s system memory and the ISP1161A1 internal FIFO buffer RAM.
Remark: The DMA operation must be controlled by the external microprocessor system
DMA controller (Master).
Fig 8.
Programmed I/O interface between a microprocessor and an ISP1161A1.
Rev. 04 — 29 January 2009
PROCESSOR
MICRO-
D [ 15:0 ]
IRQ1
IRQ2
WR
RD
CS
A2
A1
USB single-chip host and device controller
P bus I/F
D [ 15:0 ]
RD
WR
CS
A1
A0
INT1
INT2
ISP1161A1
004aaa178
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
Figure 8
shows the
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