ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 18

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
8.5 FIFO buffer RAM access by DMA mode
The DMA interface between a microprocessor and the ISP1161A1 is shown in
When doing a DMA transfer, at the beginning of every burst the ISP1161A1 outputs a
DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC).
After receiving this signal, the microprocessor will reply with a DMA acknowledge via the
DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA
transfer through the data bus. In the DMA mode, the microprocessor must issue a read or
write signal to the ISP1161A1 RD or WR pin. The ISP1161A1 will repeat the DMA cycles
until it receives an EOT signal to terminate the DMA transfer.
The ISP1161A1 supports both external and internal EOT signals. The external EOT signal
is received as input on pin EOT, and generally comes from the external microprocessor.
The internal EOT signal is generated by the ISP1161A1 internally.
To select either EOT method, set the appropriate DMA configuration register (see
Section 10.4.2
of the HcDMAConfiguration register (21H to read, A1H to write) to logic 1 will enable the
DMA counter for DMA transfer. When the DMA counter reaches the value of the
HcTransferCounter register, the internal EOT signal will be generated to terminate the
DMA transfer.
The ISP1161A1 supports either single-cycle DMA operation or burst mode DMA
operation; see
Fig 17. DMA transfer in single-cycle mode.
N = 1/2 byte count of transfer data.
RD or WR
D [ 15:0 ]
DREQ
DACK
EOT
and
Figure 17
Section
Rev. 04 — 29 January 2009
data #1
and
13.1.6). For example, for the HC, setting DMACounterSelect
Figure
data #2
18.
USB single-chip host and device controller
data #N
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
004aaa103
Figure
17 of 140
9.