ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 95

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 82.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcHardwareConfiguration register: bit allocation
DAKOLY
reserved
R/W
R/W
15
0
7
0
Table 83.
Bit
15
14
13
12
11 to 8
7
6
5
4
3
DRQPOL
EXTPUL
R/W
R/W
14
0
6
1
DcHardwareConfiguration register: bit description
Symbol
-
EXTPUL
NOLAZY
CLKRUN
CLKDIV[3:0]
DAKOLY
DRQPOL
DAKPOL
EOTPOL
WKUPCS
NOLAZY
DAKPOL
R/W
R/W
13
1
5
0
Rev. 04 — 29 January 2009
Description
reserved
A logic 1 indicates that an external 1.5 k pull-up resistor is used
on pin D+ and that SoftConnect is not used. Bus reset value:
unchanged.
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP in
the DcMode register. Bus reset value: unchanged.
A logic 1 indicates that the internal clocks are always running, even
during ‘suspend’ state. A logic 0 switches off the internal oscillator
and PLL, when they are not needed. During ‘suspend’ state this bit
must be made logic 0 to meet the suspend current requirements.
The clock is stopped after a delay of approximately 2 ms, following
the setting of bit GOSUSP in the DcMode register. Bus reset value:
unchanged.
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in MHz is
given by 48 / (N + 1). The clock frequency range is
3 MHz to 48 MHz (N = 0 to 15) with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
A logic 1 selects DACK-only DMA mode. A logic 0 selects
8237 compatible DMA mode. Bus reset value: unchanged.
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Selects DACK2 pin signal polarity (0 = active LOW). Bus reset
value: unchanged.
Selects EOT pin signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
A logic 1 enables remote wake-up via a LOW level on input pin CS
(V
unchanged.
CLKRUN
EOTPOL
BUS
R/W
R/W
12
0
4
0
must be present for wake-up on CS). Bus reset value:
WKUPCS
USB single-chip host and device controller
R/W
R/W
11
0
3
0
50 %) during ‘suspend’ state. A logic 0
PWROFF
R/W
R/W
10
0
2
0
CLKDIV[3:0]
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
INTLVL
R/W
R/W
9
1
1
0
INTPOL
R/W
R/W
94 of 140
8
1
0
0