ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 51

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 16.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable register: bit allocation
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
reserved
R/W
R/W
MIE
31
23
15
0
7
0
Table 17.
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Thus, writing a logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing a logic 0 to a bit in
this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On
a read, the current value of the HcInterruptEnable register is returned.
Bit
31
30 to 7
6
5
4
3
2
1
0
RHSC
R/W
R/W
30
22
14
0
6
0
HcInterruptEnable register: bit description
Symbol
MIE
-
RHSC
FNO
UE
RD
SF
-
SO
FNO
R/W
R/W
29
21
13
0
5
0
Rev. 04 — 29 January 2009
Description
MasterInterruptEnable by the HCD: A logic 0 is ignored by the HC. A
logic 1 enables interrupt generation by events specified in other bits of
this register.
reserved
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
0 — ignore
1 — enable interrupt generation due to Frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
0 — ignore
1 — enable interrupt generation due to Resume Detect
0 — ignore
1 — enable interrupt generation due to Start of Frame
reserved
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
R/W
R/W
UE
28
20
12
0
4
0
reserved
reserved
R/W
R/W
00H
00H
reserved
USB single-chip host and device controller
R/W
R/W
RD
27
19
11
0
3
0
R/W
R/W
SF
26
18
10
0
2
0
ISP1161A1
reserved
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
25
17
0
9
1
0
R/W
R/W
SO
50 of 140
24
16
0
8
0
0