ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 137

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

27. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Microprocessor access to a HC or a DC via an
Fig 11. Microprocessor access to internal control
Fig 12. 16-bit register access cycle.. . . . . . . . . . . . . . . . .15
Fig 13. 32-bit register access cycle.. . . . . . . . . . . . . . . . .15
Fig 14. Accessing HC control registers.. . . . . . . . . . . . . .15
Fig 15. Accessing DC control registers.. . . . . . . . . . . . . .16
Fig 16. Internal FIFO buffer RAM access cycle. . . . . . . .16
Fig 17. DMA transfer in single-cycle mode. . . . . . . . . . . .17
Fig 18. DMA transfer in burst mode. . . . . . . . . . . . . . . . .18
Fig 19. Interrupt pin operating modes. . . . . . . . . . . . . . . .19
Fig 20. HC interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . .20
Fig 21. DC interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . .22
Fig 22. Behavior of bit INTENA.. . . . . . . . . . . . . . . . . . . .22
Fig 23. ISP1161A1 HC USB states.. . . . . . . . . . . . . . . . .24
Fig 24. ISP1161A1 HC USB transaction loop. . . . . . . . . .25
Fig 25. PTD data in FIFO buffer RAM.. . . . . . . . . . . . . . .26
Fig 26. HC internal FIFO buffer RAM partitions. . . . . . . .30
Fig 27. Buffer RAM data organization.. . . . . . . . . . . . . . .31
Fig 28. PTD data with DWORD alignment in buffer
Fig 29. PIO access to internal FIFO buffer RAM. . . . . . .33
Fig 30. HC time domain behavior: example 1.. . . . . . . . .37
Fig 31. HC time domain behavior: example 2.. . . . . . . . .38
Fig 32. HC time domain behavior: example 3.. . . . . . . . .38
Fig 33. Use of 15 kW pull-down resistors on downstream
Fig 34. Downstream port power management scheme. .39
Fig 35. Using internal OC detection circuit. . . . . . . . . . . .40
Fig 36. Using an external OC detection circuit. . . . . . . . .41
Fig 37. ISP1161A1 suspend and resume clock scheme..42
Fig 38. Suspend and resume timing. . . . . . . . . . . . . . . . .82
Fig 39. SUSPEND and WAKEUP signals in a powered-off
Fig 40. ISP1161A1’s device controller in 8237 compatible
Fig 41. ISP1161A1’s device controller in DACK-only DMA
Fig 42. Interrupt pin waveform. . . . . . . . . . . . . . . . . . . . .95
Fig 43. Using a 5 V supply. . . . . . . . . . . . . . . . . . . . . . .108
Fig 44. Using a 3.3 V supply. . . . . . . . . . . . . . . . . . . . . .108
Fig 45. Oscillator circuit with external crystal. . . . . . . . .109
Fig 46. Oscillator circuit using external oscillator. . . . . .109
ISP1161A1_4
Product data sheet
ISP1161A1 operating as a USB device. . . . . . . . .2
ISP1161A1 operating as a stand-alone USB host. 2
ISP1161A1 operating as both USB host and device
simultaneously. . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Host controller sub-block diagram. . . . . . . . . . . . .6
Device controller sub-block diagram.. . . . . . . . . . .6
Pin configuration LQFP64.. . . . . . . . . . . . . . . . . . .7
Programmed I/O interface between a
microprocessor and an ISP1161A1. . . . . . . . . . .12
DMA interface between a microprocessor and an
ISP1161A1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
automux switch. . . . . . . . . . . . . . . . . . . . . . . . . . .14
registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
modem application. . . . . . . . . . . . . . . . . . . . . . . .82
DMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Rev. 04 — 29 January 2009
Fig 47. Oscillator and LazyClock logic. . . . . . . . . . . . . . 109
Fig 48. CLKOUT signal timing at ‘suspend’ and ‘resume’
Fig 49. Internal POR timing. . . . . . . . . . . . . . . . . . . . . . 111
Fig 50. Clock with respect to the external POR. . . . . . . 111
Fig 51. HC Programmed interface timing . . . . . . . . . . . 117
Fig 52. DC Programmed interface read timing (I/O and
Fig 53. DC Programmed interface write timing (I/O and
Fig 54. HC single-cycle DMA timing.. . . . . . . . . . . . . . . 119
Fig 55. HC burst mode DMA timing. . . . . . . . . . . . . . . . 120
Fig 56. External EOT timing for HC single-cycle DMA.. 120
Fig 57. External EOT timing for HC burst mode DMA. . 121
Fig 58. DC single-cycle DMA timing (8237 mode). . . . . 121
Fig 59. DC single-cycle DMA read timing in DACK-only
Fig 60. DC single-cycle DMA write timing in DACK-only
Fig 61. EOT timing in DC single-cycle DMA. . . . . . . . . 123
Fig 62. DC burst mode DMA timing. . . . . . . . . . . . . . . . 124
Fig 63. EOT timing in DC burst mode DMA. . . . . . . . . . 124
Fig 64. Typical interface circuit to Hitachi SH-3 (SH7709)
Fig 65. ISP1161A1 software model for DSC
Fig 66. Load impedance for pins D_DP and D_DM. . . . 128
Fig 67. LQFP64 (SOT314-2) package outline. . . . . . . . 129
Fig 68. LQFP64 (SOT414-1) package outline. . . . . . . . 130
Fig 69. Temperature profiles for large and small
for DC.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8237 compatible DMA).. . . . . . . . . . . . . . . . . . . 118
8237 compatible DMA).. . . . . . . . . . . . . . . . . . . 118
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
RISC processor. . . . . . . . . . . . . . . . . . . . . . . . . 125
application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
USB single-chip host and device controller
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
136 of 140