ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 32

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
9.4.2 Data organization
PTD data is used for every data transfer between a microprocessor and the USB bus, and
the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the payload data
is placed just after the PTD, after which the next PTD is placed. For an IN transfer, RAM
space is reserved for receiving a number of bytes that is equal to the total bytes of the
transfer. After this, the next PTD and its payload data are placed (see
Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD
data is put into ITL buffer RAM, and the ISP1161A1 takes care of the Ping-Pong action for
the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD (double- word
or 4-byte) alignment. This means that the memory address is organized in blocks of
4 bytes. Therefore, the first byte of every PTD and the first byte of every payload data are
located at an address which is a multiple of 4.
the first payload data is 14 bytes long, meaning that the last byte of the payload data is at
the location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore, the
first byte of the next PTD will be located at the next multiple-of-four address, 18H.
Fig 27. Buffer RAM data organization.
Rev. 04 — 29 January 2009
bottom
top
payload data of OUT transfer
payload data of OUT transfer
empty space for IN total data
PTD of OUT transfer
PTD of OUT transfer
PTD of IN transfer
RAM buffer
USB single-chip host and device controller
Figure 28
MGT952
illustrates an example in which
000H
7FFH
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
Figure
27).
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