ISP1161A1BD,151 STEricsson, ISP1161A1BD,151 Datasheet - Page 23

• Manufacturer Part Number: ISP1161A1BD,151
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,151

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1161A1_4
Product data sheet
8.6.3.1 Interrupt control
In isochronous mode, an interrupt is issued upon each packet transaction. The firmware
must take care of timing synchronization with the host. This can be done via the Pseudo
Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the DcInterruptEnable
register. If a Start-Of-Frame is lost, PSOF interrupts are generated every 1 ms. This allows
the firmware to keep data transfer synchronized with the host. After 3 missed SOF events,
the DC will enter ‘suspend’ state.
An alternative way of handling isochronous data transfer is to enable both the SOF and
the PSOF interrupts and disable the interrupt for each isochronous endpoint.
Bit INTENA in the DcMode register is a global enable/disable bit. The behavior of this bit
is given in
Fig 21. DC interrupt logic.
Fig 22. Behavior of bit INTENA.
Pin INT2: HIGH = de-assert; LOW = assert (individual interrupts are enabled).
DcInterruptEnable register
Figure
DcInterrupt register
RESUME
IEP0OUT
SUSPND
EP0OUT
IERESM
IESUSP
RESET
IEP0IN
EP0IN
IERST
IESOF
IEEOT
IEP14
EP14
22.
SOF
EOT
. . .
. . .
INT2 pin
occurs. For example,
Rev. 04 — 29 January 2009
an interrupt event
(during this time,
SOF asserted.)
INTENA = 0
. .
.
. .
.
MGT946
A
. .
.
. .
.
SOF asserted
INTENA = 1
DcMode register
USB single-chip host and device controller
INTENA
B
LE
SOF asserted
INTENA = 0
C
LATCH
004aaa198
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
INT2
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