ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 85

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

24. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
8
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
8.6.1
8.6.2
9
9.1
9.2
9.3
9.3.1
9.4
9.4.1
9.4.2
9.4.3
9.5
9.5.1
9.5.2
9.6
9.7
9.8
9.8.1
9.8.2
9.9
9.9.1
9.9.2
9.9.2.1
9.9.2.2
9.9.2.3
10
10.1
10.1.1
10.1.2
10.1.3
ISP1160-01_7
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 8
Microprocessor bus interface. . . . . . . . . . . . . . 8
Host Controller (HC) . . . . . . . . . . . . . . . . . . . . 16
HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8
Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8
Analog transceivers . . . . . . . . . . . . . . . . . . . . . 8
ST-Ericsson Serial Interface Engine (SIE) . . . . 8
Programmed I/O (PIO) addressing mode . . . . . 8
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control registers access by PIO mode . . . . . . 10
I/O port addressing . . . . . . . . . . . . . . . . . . . . . 10
Register access phases . . . . . . . . . . . . . . . . . 10
FIFO buffer RAM access by PIO mode . . . . . 11
FIFO buffer RAM access by DMA mode . . . . 12
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt output pin (INT) . . . . . . . . . . . . . . . . 14
HC’s four USB states . . . . . . . . . . . . . . . . . . . 16
Generating USB traffic . . . . . . . . . . . . . . . . . . 17
PTD data structure . . . . . . . . . . . . . . . . . . . . . 18
PTD data header definition . . . . . . . . . . . . . . . 19
HC’s internal FIFO buffer RAM structure . . . . 21
Partitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data organization . . . . . . . . . . . . . . . . . . . . . . 23
Operation and C program example . . . . . . . . 24
HC operational model . . . . . . . . . . . . . . . . . . . 28
Time domain behavior . . . . . . . . . . . . . . . . . . 29
Control transaction limitations. . . . . . . . . . . . . 30
Microprocessor loading . . . . . . . . . . . . . . . . . 30
Internal pull-down resistors for downstream
ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Overcurrent detection and power switching
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Using an internal OC detection circuit . . . . . . 32
Using an external OC detection circuit . . . . . . 33
Suspend and wake-up . . . . . . . . . . . . . . . . . . 33
HC suspended state . . . . . . . . . . . . . . . . . . . . 33
HC wake-up from suspended state . . . . . . . . 34
Wake-up by pin H_WAKEUP . . . . . . . . . . . . . 34
Wake-up by pin CS_N (software wake-up). . . 35
Wake-up by USB devices . . . . . . . . . . . . . . . . 35
HC control and status registers . . . . . . . . . . . 36
HcRevision register (R: 00H) . . . . . . . . . . . . . 36
HcControl register (R/W: 01H/81H) . . . . . . . . 37
HcCommandStatus register (R/W: 02H/82H) . 38
Rev. 07 — 29 September 2009
10.1.4
10.1.5
10.1.6
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.5
10.5.1
10.5.2
10.5.3
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
11
12
13
14
15
16
17
17.1
17.2
17.2.1
17.2.2
17.2.3
17.2.4
18
18.1
18.2
18.3
19
Power supply. . . . . . . . . . . . . . . . . . . . . . . . . . 67
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 67
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . 68
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 69
Recommended operating conditions . . . . . . 69
Static characteristics . . . . . . . . . . . . . . . . . . . 70
Dynamic characteristics. . . . . . . . . . . . . . . . . 72
Application information . . . . . . . . . . . . . . . . . 77
Test information . . . . . . . . . . . . . . . . . . . . . . . 79
HcInterruptStatus register (R/W: 03H/83H) . . 39
HcInterruptEnable register (R/W: 04H/84H). . 40
HcInterruptDisable register (R/W: 05H/85H) . 42
HC frame counter registers . . . . . . . . . . . . . . 43
HcFmInterval register (R/W: 0DH/8DH) . . . . . 43
HcFmRemaining register (R: 0EH) . . . . . . . . 44
HcLSThreshold register (R/W: 11H/91H) . . . . 46
HC Root Hub registers. . . . . . . . . . . . . . . . . . 46
HcRhDescriptorA register (R/W: 12H/92H) . . 47
HcRhDescriptorB register (R/W: 13H/93H) . . 48
HcRhPortStatus[1:2] (R/W [1]:15H/95H, [2]:
16H/96H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
HC DMA and interrupt control registers . . . . . 55
HcHardwareConfiguration register (R/W:
20H/A0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HcDMAConfiguration register (R/W: 21H/A1H) 57
HcTransferCounter register (R/W: 22H/A2H). 57
HcmPInterrupt register (R/W: 24H/A4H) . . . . 58
HcmPInterruptEnable register
(R/W: 25H/A5H) . . . . . . . . . . . . . . . . . . . . . . . 59
HC miscellaneous registers . . . . . . . . . . . . . . 60
HcChipID register (R: 27H) . . . . . . . . . . . . . . 60
HcScratch register (R/W: 28H/A8H) . . . . . . . 61
HC buffer RAM control registers . . . . . . . . . . 62
HcITLBufferLength register (R/W: 2AH/AAH) 62
HcATLBufferLength register (R/W: 2BH/ABH) 62
HcBufferStatus register (R: 2CH) . . . . . . . . . . 63
HcReadBackITL0Length register (R: 2DH) . . 64
HcReadBackITL1Length register (R: 2EH) . . 64
HcITLBufferPort register (R/W: 40H/C0H) . . . 65
Programmed I/O timing . . . . . . . . . . . . . . . . . 73
DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Single-cycle DMA timing . . . . . . . . . . . . . . . . 74
External EOT timing for single-cycle
DMASETUP . . . . . . . . . . . . . . . . . . . . . . . . . . 76
External EOT timing for burst mode DMA . . . 76
Typical interface circuit. . . . . . . . . . . . . . . . . . 77
Interfacing a ISP1160/01 to a SH7709 RISC
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical software model . . . . . . . . . . . . . . . . . 78
HcFmNumber register (R: 0FH). . . . . . . . . . . 45
HcRhStatus register (R/W: 14H/94H). . . . . . . 49
HcSoftwareReset register (W: A9H) . . . . . . . 61
HcATLBufferPort register (R/W: 41H/C1H) . . 65
Burst mode DMA timing . . . . . . . . . . . . . . . . . 75
Embedded USB host controller
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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