ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 78
ISP1160BD/01
Manufacturer Part Number
ISP1160BD/01
Description
Manufacturer
STEricsson
Datasheet
1.ISP1160BD01.pdf
(87 pages)
Specifications of ISP1160BD/01
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ISP1160-01_7
Product data sheet
18.3 Typical software model
Remark: SH7709’s system clock input is for reference only. Refer to SH7709’s
specification for its actual use.
The ISP1160/01 can work under either 3.3 V or 5.0 V power supply; however, its internal
core works at 3.3 V. When using 3.3 V as the power supply input, the internal DC/DC
regulator will be bypassed. It is best to connect all four power supply pins (V
V
of the ISP1160/01’s I/O pins are 5 V-tolerant. This feature allows the ISP1160/01 the
flexibility to be used in an embedded system under either a 3.3 V or a 5 V power supply.
A typical SH7709 interface circuit is shown in
This section shows a typical software requirement for an embedded system that
incorporates the ISP1160/01. The software model for a Digital Still Camera (DSC) is used
as the example for illustration (as shown in
Class driver and device driver, both of which provide API for application tasks for host
function.
•
•
•
•
HOLD1
There is a DMA channel standard control line: DREQ and DACK_N. The DREQ signal
has programmable active levels.
An interrupt line INT is used by the HC. It has programmable level/edge and polarity
(active HIGH or LOW).
The internal 15 kΩ pull-down resistors are used for the HC’s two USB downstream
ports.
The RESET_N signal is active LOW.
and V
HOLD2
) to the 3.3 V power supply (for more information, see
Rev. 07 — 29 September 2009
Figure
Figure
41). The host stack provides API for
40.
Embedded USB host controller
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
Section
CC
, V
REG(3V3)
11). All
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