ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 44

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 22.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcFmRemaining register: bit allocation
10.2.2 HcFmRemaining register (R: 0EH)
FRT
31
23
15
R
R
R
R
0
0
0
7
0
reserved
Table 21.
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in
the current frame.
Code (Hex): 0E — read
Bit
31
30 to 16
15 to 14
13 to 0
30
22
14
R
R
R
R
0
0
0
6
0
HcFmInterval register: bit description
Symbol
FIT
FSMPS
[14:0]
-
FI[13:0]
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 07 — 29 September 2009
Description
FrameIntervalToggle: The HCD toggles this bit whenever it loads a
new value to FrameInterval.
FSLargestDataPacket: Specifies a value which is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits which can
be sent or received by the HC in a single transaction at any given time
without causing a scheduling overrun. The field value is calculated by
the HCD.
reserved
FrameInterval: Specifies the interval between two consecutive SOFs
in bit times. The default value is 11999. The HCD must save the
current value of this field before resetting the HC. Setting the
HostControllerReset field of the HcCommandStatus register will cause
the HC to reset this field to its default value. HCD may choose to
restore the saved value upon completing the reset sequence.
28
20
12
R
R
R
R
0
0
0
4
0
reserved
FR[7:0]
reserved
27
19
11
R
R
R
R
0
0
0
3
0
FR[13:8]
Embedded USB host controller
26
18
10
R
R
R
R
0
0
0
2
0
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
25
17
R
R
R
R
0
0
9
0
1
0
24
16
R
R
R
R
0
0
8
0
0
0
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