ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 29

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
Fig 21. HC time domain behavior: example 1.
SOF
interrupt
ISO
9.5.1 Time domain behavior
(frame N)
For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This will
cause the HcBufferStatus register to show that the ITL0 buffer is full by setting
bit ITL0BufferFull to logic 1. At this stage, the HCD cannot write ISO data into the ITL0
buffer RAM again.
In the second frame, the HC will process the ISO_A data in the ITL0 buffer. At the same
time, the HCD can write ISO_B data into the ITL1 buffer. When the next SOF comes (the
beginning of the third frame), both ITL1BufferFull and ITL0BufferDone are automatically
set to logic 1.
In the third frame, the HCD has to read at least two bytes (one word) of the ITL0 buffer to
clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not cleared, when the
next SOF comes (the beginning of the fourth frame) the ITL0BufferDone and
ITL0BufferFull bits will be cleared automatically. This also applies to the ITL1 buffer
because ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a
power-on reset or software reset will have to be applied.
In example 1
before the next interrupt. Note that on the ISO interrupt of frame N:
In example 2
the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no AT traffic
in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The AT part is
simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer mechanism is
back to the normal operation. This simple mechanism ensures, among other things, that
Control transfers are not dropped systematically from the USB in case of an overloaded
microprocessor.
read ISO_A(N − 1) write ISO_A(N + 1)
•
•
The ISO packet for frame N + 1 will be written
The AT packet for frame N + 1 will be written.
on USB
traffic
(Figure
(Figure
interrupt
AT
(frame N + 1)
Rev. 07 — 29 September 2009
21), the CPU is fast enough to read back and download a scenario
22), the microprocessor is still busy transferring the AT data when
read AT(N)
(frame N + 2)
write AT(N + 1)
Embedded USB host controller
(frame N + 3)
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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