ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 56

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 36.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcHardwareConfiguration register: bit allocation
EOTInput
Polarity
R/W
R/W
15
0
7
0
Table 37.
Bit
15 to 13 -
12
11
10
9
8
7
6
5
4 to 3
2
1
0
DACKInput
reserved
Polarity
R/W
R/W
14
0
6
0
Symbol
2_DownstreamPort15Kr
esistorsel
SuspendClkNotStop
AnalogOCEnable
-
DACKMode
EOTInputPolarity
DACKInputPolarity
DREQOutputPolarity
DataBusWidth[1:0]
InterruptOutputPolarity
InterruptPinTrigger
InterruptPinEnable
HcHardwareConfiguration register: bit description
Polarity
Output
DREQ
R/W
R/W
13
0
5
1
Rev. 07 — 29 September 2009
resistorsel
2_Down
Port15K
stream
DataBusWidth[1:0]
R/W
R/W
12
0
4
0
This bit is used as pin INT’s master interrupt enable and
Description
reserved
0 — use external 15 kΩ resistors for downstream ports
1 — use built-in resistors for downstream ports
0 — clock can be stopped
1 — clock can not be stopped
0 — use external OC detection; digital input
1 — use on-chip OC detection; analog input
reserved
0 — normal operation; pin DACK_N is used with read and
write signals
1 — reserved
0 — active LOW
1 — active HIGH
0 — active LOW
1 — reserved
0 — active LOW
1 — active HIGH
These bits are fixed at logic 0 and logic 1 for the ISP1160/01.
01 — 16 bits
Others — reserved
0 — active LOW
1 — active HIGH
0 — interrupt is level-triggered
1 — interrupt is edge-triggered
should be used together with register HcμPInterruptEnable to
enable pin INT.
0 — pin INT is disabled
1 — pin INT is enabled
ClkNotStop
Suspend
R/W
R/W
11
0
3
1
AnalogOC
Interrupt
Polarity
Enable
Output
Embedded USB host controller
R/W
R/W
10
0
2
0
ISP1160/01
PinTrigger
reserved
Interrupt
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
9
0
1
0
InterruptPin
DACKMod
Enable
R/W
R/W
8
e
0
0
0
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