ISP1160BD/01 STEricsson, ISP1160BD/01 Datasheet - Page 30

• Manufacturer Part Number: ISP1160BD/01
• Manufacturer: STEricsson

Specifications of ISP1160BD/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1160-01_7
Product data sheet
Fig 22. HC time domain behavior: example 2.
Fig 23. HC time domain behavior: example 3.
9.5.2 Control transaction limitations
(frame N)
(frame N)
9.6 Microprocessor loading
9.7 Internal pull-down resistors for downstream ports
In example 3
of the next frame has occurred. This will result in undefined behavior for the ISO data on
the USB bus in frame N + 1 (depending on whether the exact timing data is corrupted or
not). The HC should not raise an AT interrupt in frame N + 1.
The different phases of a Control transfer (SETUP, Data and Status) should never be put
in the same ATL.
The maximum amount of data that can be transferred for an endpoint in one frame is
1023 bytes. The number of USB packets that are needed for this batch of data depends
on the maximum packet size that is specified.
The HCD has to schedule the transactions in a frame. On the other hand, the
microprocessor must have the ability to handle the interrupts coming from the HC every
1 ms. It must also be able to do the scheduling for the next frame, reading the frame
information from and writing the next frame information to the buffer RAM in the time
between the end of the current frame and the start of the next frame.
There are four internal 15 kΩ pull-down resistors built in the ISP1160/01 for the two
downstream ports: two resistors for each port. These resistors are software selectable by
programming bit 12 (2_DownstreamPort15Kresistorsel) of the HcHardwareConfiguration
register (20H to read, A0H to write). When bit 12 is logic 0, external 15 kΩ pull-down
resistors are used. When bit 12 is logic 1, internal 15 kΩ pull-down resistors are used.
See
This feature is a cost-saving option. However, the power-on reset default value of bit 12 is
logic 0. If using the internal resistors, the HCD must check this bit status after every reset,
because a reset action (hardware or software) will clear this bit.
Figure
24.
(Figure
(frame N + 1)
(frame N + 1)
Rev. 07 — 29 September 2009
23), the ISO part is still being written while the Start of Frame (SOF)
(frame N + 2)
(frame N + 2)
Embedded USB host controller
(frame N + 3)
(frame N + 3)
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
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