M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 80

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(3) EPi_ACLR (OUT Buffer Auto-Clear Mode) Bit (b11)
(5) EPi_Octl (Register 8-Bit Mode) Bit (b10)
(6) EPi_MXPS (Maximum Packet Size) Bits (b9~b0)
This bit is valid at continuous transmit/receive mode (EPi_RWMD bit = “1”) when set to IN buffer (EPi_DIR
bit = “1”). Set to “0” for the other modes.
In case of the completion of SIE side buffer transmit, if the IVAL bit is set to “0”, the zero-length packet
automatically transmitted in the last under the condition as follows:
In case of the continuous transmit/receive mode, the data equivalent to the size set by the EPi_MXPS bits is
automatically transmitted several times before transmitting the data equivalent to the size set by the
EPi_Buf_siz bit.
When set to OUT buffer (EPi_DIR bit = “0”), all buffers both of CPU and SIE sides are cleared by setting “1” to
this bit.
This bit does not get automatically cleared to “0” even after the buffers are cleared.
When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is not executed against the
received OUT token. Instead, the ACK response is sent to the host after receiving the data. The received data
is not written to the buffer. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is
executed.
When set to IN buffer (EPi_DIR bit = “1”), only the SIE side buffer and the buffer with the writing completed
(the buffer when IVAL bit = “1”) are cleared by setting “1” to this bit.
When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is given against the received IN
token. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is executed.
This bit has the same function as the Octl bit of the CPU_FIFO Select Register or the Octl bit of the Dn_FIFO
Select Register. Please refer to the items of these registers.
These bits set the upper limit (byte count) of the data transmitted and received in one packet transfer.
Set the wMaxPacketSize value transmitted to the host.
In case of transmitting, the data equivalent to the size set by these bits is read out from the buffer for transmit.
If the buffer does not have the data equivalent to the set by these bits, the data is transmitted as the short
packet.
In case of receiving, the received data equivalent to the size set by these bits is written to the buffer. In case
the received data exceeds the size set by these bits, the following bit is set to "1":
2 0 0 4 . 1 1 . 0 1
Note:
Note:
•
•
When set to IN buffer, make sure to set the response PID to NAK (EPi_PID bits = “00”) before setting this bit to
“1”.
Set this bit after setting the response PID to NAK (EPi_PID bits = “00”).
When the buffer size set by the EPi_Buf_siz bit is the integral multiple of the size set by the
EPi_MXPS bits.
The EPB_EMP_OVR bit
(buffer empty/size-over error interrupt occurs when the EPB_EMPE bit is set to “1”).
p a g e 8 0 o f 1 2 2