M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 70

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
2.34 DMAn_Transaction Count Registers (n=0~1)
R e v 1 . 0 1
(1) TRNCNT (Transaction Count) Bits (b15~b0)
b15
15~0
DMA0_Transaction Count Register (DMA0_TRN_COUNT)
DMA1_Transaction Count Register (DMA1_TRN_COUNT)
0
-
-
b
This register is used under the following conditions:
With the transaction count function set to be enabled (TREN bit = “1”), the following conditions are added to
the buffer receive completion condition. In case of the receive completion, refer to the “EPi_RWMD bit of the
EPi Configuration Register 0”.
This register is composed of two registers as follows:
It is necessary to clear the TNCNT bits as the current register to “0” by writing “1” to the TRCLR bit before the
next transfer.
2 0 0 4 . 1 1 . 0 1
TRNCNT
Transaction Count
14
0
-
-
•
•
•
•
•
•
•
When set to OUT buffer (EPi_DIR bit = ”0”).
When set to continuous receive mode (EPi_RWMD bit = ”1”).
When set to bulk transfer mode (EPi_TYP bits = ” 01”)
When accessing using Dn_FIFO Data Register.
When the value set by this register conforms to the packet receive count.
(Conformity between current register and compare register; See below.)
Current register
Compare register
13
0
-
-
p a g e 7 0 o f 1 2 2
12
0
-
-
Bit name
11
0
-
-
:Counting of the received packet number (counts up at the TREN bit = “1”)
:The value that completes the receiving
10
0
-
-
9
0
-
-
<TREN bit = "0">
Packet count that completes the receiving
(behaving as the compare register)
<TREN bit = "1">
The number of the received packets (behaving as the current
register)
Packet count that completes the receiving
(behaving as the compare register)
Read
Write
8
0
-
-
TRNCNT
7
0
-
-
6
0
-
-
Function
5
0
-
-
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0000>
<Address : H’4E>
<Address : H’56>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
b0
0
-
-
W