M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 51

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(4) E0req (EP0_FIFO Ready) Bit (b11)
(5) CCPL (Control Transfer Control) Bit (b10)
(6) ODLN (Control Write Receive Data Length) Bits (b8~b0)
When this bit is equal to “1”, this bit indicates the states as follows:
Make sure that this bit is equal to “0” before accessing the aforesaid registers/bits.
This bit controls the status stage of the control transfer.
When this bit is set to “1”, the operations below are executed at status stage of the control transfer and notifies
the normal completion of the control transfer:
When this bit is set to “0”, NAK response is executed to the host after receiving the IN token/OUT token at
status stage of the control transfer.
This bit is automatically cleared to “0” by receiving the setup token.
These bits are valid for control write transfer and indicate the data number (byte count) received from the
CPU side buffer.
Further, these bits are set to execute countdown when the EP0_FIFO Data Register is read out. This
operation changes according to the RCNT bit. For details, refer to “RCNT bit”.
These bits indicate the valid value when the E0req bit of this register is equal to “0”.
2 0 0 4 . 1 1 . 0 1
Note:
Note:
When set to control write transfer (ISEL bit = “0”)
When set to control read transfer (ISEL bit = “1”)
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Refer to “3.2 FIFO Buffer” for CPU/SIE side.
In case the transmit data exists in the buffer for EP0_FIFO, the buffer empty interrupt occurs in the concerned
endpoint when “1” is written to the BCLR bit.
EP0_FIFO Data Register can not be accessed.
The IVAL bit value of this register is invalid.
The ODLN bit values of this register are invalid.
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p a g e 5 1 o f 1 2 2
Transmits the zero-length packet after receiving IN token if the EP0_PID bits are set to “01”.
ACK response to the host after receiving the zero-length packet following OUT token if the
EP0_PID bits are set to “01”.