M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 33

• Manufacturer Part Number: M66291GP#201
• Description: IC USB CONTROLLER GEN-PUR 48LQFP
• Manufacturer: Renesas Electronics America

Specifications of M66291GP#201

• Package / Case: 48-LQFP
• Mounting Type: Surface Mount
• Current - Supply: 30mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Interface: Serial
• Controller Type: USB 2.0 Controller
• Lead Free Status / RoHS Status: Not Compliant

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(12) CTSQ (Control Transfer Stage) Bits (b2~b0)
These bits indicate the present stage in the control transfer. Refer to Figure 2.7.
The control transfer sequence error is described below. When this error occurs, the EP0_PID bits are set to
“1x” (stall state).
control write transfer, it is not recognized as the control transfer sequence error.
2 0 0 4 . 1 1 . 0 1
: CTRT interrupt has occurred
In case the amount of received data exceeds the wLength value in the request at the data stage of the
(1) Setup stage completion
(2) Control read transfer
(3) Control write transfer
(4) Control transfer completion
(5) Control transfer
<At control read transfer>
<At control write transfer>
<At control write no data transfer>
<Others>
status stage transition
status stage transition
sequence error
[CTSQ bits ="000"]
000 : Idle or Setup Stage
001 : Control Read Transfer Data Stage
010 : Control Read Transfer Status Stage
011 : Control Write Transfer Data Stage
100 : Control Write Transfer Status Stage
101 : Control Write No Data Transfer Status Stage
110 : Control Transfer Sequence Error (refer to below)
111 : Reserved
Setup stage
•
•
•
•
•
•
•
p a g e 3 3 o f 1 2 2
Setup token receive
OUT token is received when data is never transferred against the IN token of the data stage.
IN token is received at status stage.
Data packet other than the zero-length packet is received at status stage.
IN token is received when ACK response is never made against the OUT token of the data
stage.
OUT token is received in status stage.
OUT token is received in status stage.
Data exceeding in size set by the EP0 Packet Size Register is received (the EPB_EMP_OVR
bit of the Interrupt Status Register 3 is set to “1”).
ACK transmit
ACK transmit
transmit
ACK
(1)
Setup token receive
(1)
Figure 2.7 Control Transfer Transition
Note : When the SERR bit is set to "1" and the control transfer sequence error causes the CTRT interrupt to
[CTSQ bits ="001"]
[CTSQ bits ="011"]
Control write
Control read
data stage
data stage
Further, even after the completion of the next set up stage, the CTRT interrupt due to the completion
occur, the CTSQ bit values (1xx) are retained until "0" is written to the CTRT bit (interrupt is cleared).
of the set up stage is not occurred until "0" is written to the CTRT bit.
When the SERR bit is set to "0", if setup token is received, the CTSQ bits changes to "000".
transfer
transfer
Setup token receive
[CTSQ bits ="1xx"]
IN token receive
Control transfer
sequence error
OUT token
receive
(Note )
(2)
(1)
(3)
[CTSQ bits ="010"]
[CTSQ bits ="100"]
[CTSQ bits ="101"]
transfer no data
(5)
Control write
Control write
Control read
status stage
status stage
status stage
transfer
transfer
Error detection
receive
ACK transmit
receive
ACK
ACK
(4)
[CTSQ bits ="000"]
Idle stage