FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 102
FDC37B787-NS
Manufacturer Part Number
FDC37B787-NS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.FDC37B787-NS.pdf
(249 pages)
Specifications of FDC37B787-NS
Pin Count
128
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FDC37B787-NS
Manufacturer:
Standard
Quantity:
36
Company:
Part Number:
FDC37B787-NS
Manufacturer:
Microsemi
Quantity:
421
Company:
Part Number:
FDC37B787-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
FDC37B787-NS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 102 of 249
- Download datasheet (866Kb)
BITS [2:0] Parallel Port DMA (read-only)
Refer to Table 44C.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
BITS 7,6,5
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
0:
BIT 3 dmaEn
Read/Write
1:
0:
BIT 2 serviceIntr
Read/Write
Disables the interrupt generated on the
asserting edge of nFault.
Enables an interrupt pulse on the high to low
edge of nFault. Note that an interrupt will be
generated if nFault is asserted (interrupting)
and this bit is written from a 1 to a 0. This
prevents interrupts from being lost in the time
between the read of the ecr and the write of
the ecr.
Enables DMA (DMA starts when serviceIntr is
0).
Disables DMA unconditionally.
102
1:
0:
case dmaEn=1:
case dmaEn=0 direction=0:
case dmaEn=0 direction=1:
BIT 1 full
Read only
1:
0:
BIT 0 empty
Read only
1:
0:
Disables DMA and all of the service
interrupts.
Enables one of the following 3 cases of
interrupts. Once one of the 3 service
interrupts has occurred serviceIntr bit shall be
set to a 1 by hardware. It must be reset to 0 to
re-enable the interrupts. Writing this bit to a 1
will not cause an interrupt.
During DMA (this bit is set to a 1 when
terminal count is reached).
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the
FIFO.
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be
read from the FIFO.
The FIFO cannot accept another byte or the
FIFO is completely full.
The FIFO has at least 1 free byte.
The FIFO is completely empty.
The FIFO contains at least 1 byte of data.
Related parts for FDC37B787-NS
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
USB CHIP
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
ULTRA FAST USB 2.0 MULTI-SLOT FLASH MEDI
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet:
Part Number:
Description:
Manufacturer:
Standard Microsystems (SMSC)
Datasheet: