NAND256W3A2BN6F NUMONYX, NAND256W3A2BN6F Datasheet - Page 17

• Manufacturer Part Number: NAND256W3A2BN6F
• Manufacturer: NUMONYX

Specifications of NAND256W3A2BN6F

• Cell Type: NAND
• Density: 256Mb
• Access Time (max): 12us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 32M
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

NAND128-A, NAND256-A
3.6
3.7
3.8
3.9
3.10
Read Enable (R)
Read Enable, R, controls the sequential data output during read operations. Data is valid
t
address counter by one.
Write Enable (W)
The Write Enable input, W, controls writing to the Command Interface, Input Address and
Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
Write Protect (WP)
The Write Protect pin is an input that provides hardware protection against unwanted
program or erase operations. When Write Protect is Low, V
any program or erase operations.
It is recommended to keep the Write Protect pin Low, V
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, V
operation completes Ready/Busy goes High, V
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
Refer to the
calculate the value of the pull-up resistor.
V
V
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V
(see paragraph
program/erase operations during power-transitions.
Each device in a system should have V
widths should be sufficient to carry the required program and erase currents
RLQV
DD
DD
provides the power supply to the internal core of the memory device. It is the main
after the falling edge of R. The falling edge of R also increments the internal column
supply voltage
Section 10.1: Ready/busy signal electrical characteristics
Figure 35: Data
OL
, a read, program or erase operation is in progress. When the
protection) to protect the device from any involuntary
DD
decoupled with a 0.1 µF capacitor. The PCB track
OH
.
IL
, during power-up and power-down.
IL
, the device does not accept
DD
is below the V
for details on how to
Signal descriptions
LKO
threshold
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