NAND256W3A2BN6F NUMONYX, NAND256W3A2BN6F Datasheet

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... Lead-free components are compliant with Development tools – Error correction code software and – Bad blocks management and wear leveling – File system OS native reference software – Hardware simulation models Rev 16 TSOP48 FBGA VFBGA55 1.05 mm transitions the RoHS directive hardware models algorithms 1/59 www.numonyx.com 1 ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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NAND128-A, NAND256-A 6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables List of tables Table 1. NAND128-A and NAND256-A device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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NAND128-A, NAND256-A List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Each block can be programmed and erased up to 100,000 cycles. To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). A Write Protect pin is available to provide hardware protection against program and erase operations. ...

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... Serial number (unique identifier), which enables each device to be uniquely identified subject to an NDA and is, therefore, not described in the datasheet. For more details about these security features, contact your nearest Numonyx sales office. For information on how to order these devices refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits in valid blocks erased to ’ ...

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... Ready/Busy (open-drain output) W Write Enable WP Write Protect V Supply voltage DD V Ground SS NC Not connected internally DU Do not use 8/ I/O8-I/O15, x16 E I/O0-I/O7, x8/x16 R W NAND flash Function NAND128-A, NAND256-A AI07557C Direction I/O I/O Input Input Input Input Output Input Input Supply Ground – ...

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... NAND128-A, NAND256-A Figure 2. Logic block diagram Address register/counter Command interface E logic WP R Command register NAND flash memory array P/E/R controller, high voltage generator Page buffer Y decoder I/O buffers & latches RB I/O0-I/O7, x8/x16 I/O8-I/O15, x16 Description AI07561c 9/59 ...

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... Description Figure 3. TSOP48 connections, x8 devices 10/ NAND flash (x8 NAND128-A, NAND256 I/O7 I/O6 I/O5 I/ I/O3 I/O2 I/O1 I/ AI07585C ...

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... NAND128-A, NAND256-A Figure 4. TSOP48 connections, x16 devices NAND flash (x16 Description V SS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/ I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/ AI07559C 11/59 ...

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Description Figure 5. VFBGA55 connections, x8 devices (top view through package 12/ ...

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NAND128-A, NAND256-A Figure 6. VFBGA55 connections, x16 devices (top view through package ...

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... Refer to 2.1 Bad blocks The NAND flash 528-byte/264-word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional bad blocks may develop during the lifetime of the device. The bad block information is written prior to shipping (refer to more details) ...

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NAND128-A, NAND256-A Figure 7. Memory array organization 1st half page (256 bytes) Block Page 512 bytes Page buffer, 512 bytes x8 DEVICES Block = 32 pages Page = 528 bytes (512+16) 2nd half page (256 bytes) Block Page 8 bits ...

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Signal descriptions 3 Signal descriptions See Figure 1: Logic diagram connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs input the selected address, output the data during a read operation or input a command or data during a ...

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NAND128-A, NAND256-A 3.6 Read Enable (R) Read Enable, R, controls the sequential data output during read operations. Data is valid t after the falling edge of R. The falling edge of R also increments the internal column RLQV address counter ...

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Signal descriptions 3.11 V ground SS Ground the reference for the power supply. It must be connected to the system SS, ground. 18/59 NAND128-A, NAND256-A ...

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NAND128-A, NAND256-A 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see 4.1 Command input Command input bus operations give commands to the memory. Commands are accepted when ...

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Bus operations 4.4 Data output Data output bus operations read the data in the memory array, the status register, the electronic signature, and the serial number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch ...

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NAND128-A, NAND256-A Table 7. Address insertion, x16 devices I/O8- Bus Cycle I/O15 ’don’t care’ in x16 devices. 2. Any additional address input cycles are ignored. 3. The 01h ...

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Command set 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...

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... Device operations 6.1 Pointer operations As the NAND flash memories contain two different areas for x16 devices and three different areas for x8 devices (see to the different areas of the memory array (they select the most significant column address). The Read A and Read B commands act as pointers to the main memory area. Their use depends on the bus width of the device ...

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Device operations Figure 9. Pointer operations for programming 80h I/O 00h Areas can be programmed depending on how much data is input. Subsequent 00h commands can be omitted. 80h I/O 01h Areas B, C can be programmed ...

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NAND128-A, NAND256-A and Chip Enable remains Low, then the next page is automatically loaded into the page buffer and the read operation continues. A sequential row read operation can only be used to read within a block. If the block ...

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Device operations Figure 12. Sequential row read operations (Read busy time) RB 00h/ I/O Address inputs 01h/ 50h Command code Figure 13. Sequential row read block diagrams Read A command, x8 devices Area B Area A (2nd half Page) (1st ...

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NAND128-A, NAND256-A 6.3 Page program The page program operation is the standard operation to program data to the memory array. The main area of the memory array is programmed by page, however partial page programming is allowed where any number ...

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Device operations 6.4 Copy back program The copy back program operation copies the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster ...

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NAND128-A, NAND256-A 6.5 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists ...

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Device operations After the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status register command is issued during a random read cycle a new ...

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NAND128-A, NAND256-A Refer to Table 12 Table 12. Electronic signature Part number NAND128W3A NAND256W3A NAND256W4A for information on the addresses. Manufacturer code Device operations Device code 20h 73h 20h 75h 0020h 0055h 31/59 ...

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... For the integration of NAND memories into an application, Numonyx provides a full range of software solutions such as file systems, sector managers, drivers, and code management. Contact the nearest Numonyx sales office or visit www.numonyx.com for more details. ...

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NAND128-A, NAND256-A Refer to Table 13 operation. Table 13. Block failure Operation Erase Program Read Figure 17. Bad block management flowchart for the recommended procedure to follow if an error occurs during an START Block Address = Block 0 Data ...

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Software algorithms 7.3 Garbage collection When a data page needs to be modified faster to write to the first available page, and the previous page is marked as invalid. After several updates it is necessary to remove invalid ...

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... NAND128-A, NAND256-A 7.5 Error correction code An error correction code (ECC) can be implemented in the NAND flash memories to identify and correct errors in the data. The recommendation is to implement 23 bits of ECC for every 4096 bits in the device. Figure 19. Error detection 7.6 Hardware simulation models 7 ...

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... The program and erase times and the number of program/ erase cycles per block are shown in Table 14. Table 14. Program, erase times and program erase endurance cycles Parameters Page program time Block erase time Program/erase cycles (per block) Data retention 36/59 NAND128-A, NAND256-A NAND flash Min Typ 200 2 100,000 10 Unit Max 500 µ ...

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NAND128-A, NAND256-A 9 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...

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... V devices (2 TTL GATE devices (3.0 - 3.6V devices 3 V devices ref (1)(2) Parameter Test condition Input capacitance and C are not 100% tested. IN I/O NAND128-A, NAND256-A NAND flash Min Max 2.7 3.6 – 100 0.4 2.4 1.5 5 8.35 Typ Max = Units V ° ...

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... NAND128-A, NAND256-A Figure 20. Equivalent testing circuit for AC characteristics measurement V DD NAND Flash C L GND DC and AC parameters 2R ref 2R ref GND Ai11085 39/59 ...

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DC and AC parameters Table 18. DC characteristics Symbol I DD1 Operating current I DD2 I DD3 I Standby current (TTL) DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input High ...

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NAND128-A, NAND256-A t Table 19. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable Low ALLWL t ALS t Address Latch High to Write Enable Low ALHWL t Command Latch High to ...

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DC and AC parameters Table 20. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 Ready/Busy Low ...

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NAND128-A, NAND256-A Figure 21. Command Latch AC waveforms I/O Figure 22. Address Latch AC waveforms CL tELWL (E Setup time tALHWL (AL Setup time) AL I/O tCLHWL (CL Setup time) tELWL (E Setup time) ...

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DC and AC parameters Figure 23. Data Input Latch AC waveforms CL E tALLWL (ALSetup time I/O Figure 24. Sequential data output after read AC waveforms Low Low High. 44/59 tWLWL ...

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NAND128-A, NAND256-A Figure 25. Read status register AC waveform Figure 26. Read electronic signature AC waveform I/O Read Electronic 1. Refer to Table 12: Electronic signature tALLRL1 tRLQV (Read ES Access time) Man. 90h 00h ...

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DC and AC parameters Figure 27. Page read A/read B operation AC waveform 00h or I/O 01h Command Code Figure 28. Read C operation, one page AC waveform I/O ...

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NAND128-A, NAND256-A Figure 29. Page program AC waveform I/O 80h RB Page Program Setup Code Figure 30. Block erase AC waveform I/O RB Block Erase Setup Command tWLWL tWLWL (Write ...

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DC and AC parameters Figure 31. Reset AC waveform I/O RB 10.1 Ready/busy signal electrical characteristics Figures Figure 32, Ready/Busy signal. The value required for the resistor R following equation: Therefore, where I is the sum ...

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NAND128-A, NAND256-A Figure 33. Ready/busy load circuit Figure 34. Resistor value versus waveform timings for Ready/Busy signal ° DEVICE RB Open Drain Output and AC parameters ibusy AI07563B 49/59 ...

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... DC and AC parameters 10.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD Low ( guarantee hardware protection during power transitions as shown in the below IL figure. Figure 35. Data protection V DD ...

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... NAND128-A, NAND256-A 11 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

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Package mechanical Figure 37. VFBGA55 active ball array, 0.8 mm pitch, package outline 1. Drawing is not to scale. 52/ FE1 FD1 ...

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NAND128-A, NAND256-A Table 22. VFBGA55 1. ball array, 0.8 mm pitch, package mechanical data Symbol ddd FD1 ...

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... F = RoHS compliant package, tape and reel packing 1. 1. x16 organization only available for MCP. Note: Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Numonyx sales office. 54/59 NAND128-A, NAND256-A NAND128 ...

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... NAND128-A, NAND256-A Appendix A Hardware interface examples NAND flash devices can be connected to a microcontroller system bus for code and data storage. For microcontrollers that have an embedded NAND controller the NAND flash can be connected without the addition of glue logic (see logic is required for general purpose microcontrollers that do not have an embedded NAND controller ...

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... Hardware interface examples Figure 39. Connection to microcontroller, with glue logic Microcontroller Figure 40. Building storage modules NAND Flash W Device 56/ CSn A3 CLK NAND Flash NAND Flash Device 2 Device 3 NAND128-A, NAND256 flip-flop NAND Flash I NAND Flash Device n I/O0-I/O7 or I/O0-I/O15 AI07589 E n+1 NAND Flash Device n+1 AI08331 ...

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NAND128-A, NAND256-A 13 Revision history Table 24. Document revision history Date Version 06-Jun-2003 07-Aug-2003 27-Oct-2003 03-Dec-2003 13-Apr-2004 28-May-2004 02-Jul-2004 01-Oct-2004 03-Dec-2004 1 Initial release 2 Design phase 3 Engineering phase Document promoted from Target Specification to Preliminary Data status. V ...

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... TSOP48 connections, x16 devices Removed all information pertaining to the 512-Mbit and 1-Gbit devices. 14 Applied Numonyx branding. Removed all the information pertaining the 1.8 V devices (V 15 1.95 V) and the USOP48 and VFBGA63 packages. Added the sequential row read option throughout the document. ...

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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...