MT47H32M16HR-25E:F Micron Technology Inc, MT47H32M16HR-25E:F Datasheet - Page 7
![](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-25E:F
Manufacturer Part Number
MT47H32M16HR-25E:F
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16HR-25EF.pdf
(132 pages)
Specifications of MT47H32M16HR-25E:F
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
295mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H32M16HR-25E:F
Manufacturer:
ON
Quantity:
700
Part Number:
MT47H32M16HR-25E:F
Manufacturer:
MICRON
Quantity:
20 000
512Mb: x4, x8, x16 DDR2 SDRAM
Features
Figure 51: Bank Read – Without Auto Precharge ............................................................................................. 98
Figure 52: Bank Read – with Auto Precharge ................................................................................................... 99
t
t
Figure 53: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window ................................................. 100
t
t
Figure 54: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ..................................................... 101
t
t
Figure 55: Data Output Timing –
AC and
DQSCK ......................................................................................... 102
Figure 56: Write Burst ................................................................................................................................... 104
Figure 57: Consecutive WRITE-to-WRITE ...................................................................................................... 105
Figure 58: Nonconsecutive WRITE-to-WRITE ................................................................................................ 105
Figure 59: WRITE Interrupted by WRITE ....................................................................................................... 106
Figure 60: WRITE-to-READ ........................................................................................................................... 107
Figure 61: WRITE-to-PRECHARGE ................................................................................................................ 108
Figure 62: Bank Write – Without Auto Precharge ............................................................................................ 109
Figure 63: Bank Write – with Auto Precharge ................................................................................................. 110
Figure 64: WRITE – DM Operation ................................................................................................................ 111
Figure 65: Data Input Timing ........................................................................................................................ 112
Figure 66: Refresh Mode ............................................................................................................................... 113
Figure 67: Self Refresh .................................................................................................................................. 115
Figure 68: Power-Down ................................................................................................................................ 117
Figure 69: READ-to-Power-Down or Self Refresh Entry .................................................................................. 119
Figure 70: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 119
Figure 71: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 120
Figure 72: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 120
Figure 73: REFRESH Command-to-Power-Down Entry ................................................................................. 121
Figure 74: ACTIVATE Command-to-Power-Down Entry ................................................................................ 121
Figure 75: PRECHARGE Command-to-Power-Down Entry ............................................................................ 122
Figure 76: LOAD MODE Command-to-Power-Down Entry ............................................................................ 122
Figure 77: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 123
Figure 78: RESET Function ........................................................................................................................... 125
Figure 79: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 127
Figure 80: Timing for MRS Command to ODT Update Delay .......................................................................... 128
Figure 81: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 128
Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 129
Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 129
Figure 84: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 130
Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 131
Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 132
7
PDF: 09005aef82f1e6e2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512MbDDR2.pdf - Rev. R 12/10 EN
© 2004 Micron Technology, Inc. All rights reserved.