MT48LC2M32B2P-6:G Micron Technology Inc, MT48LC2M32B2P-6:G Datasheet - Page 54

IC, SDRAM, 64MBIT, 166MHZ, TSOP-86

MT48LC2M32B2P-6:G

Manufacturer Part Number
MT48LC2M32B2P-6:G
Description
IC, SDRAM, 64MBIT, 166MHZ, TSOP-86
Manufacturer
Micron Technology Inc
Type
SDRAMr
Series
-r
Datasheets

Specifications of MT48LC2M32B2P-6:G

Organization
2Mx32
Density
64Mb
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Memory Type
DRAM - Sychronous
Access Time
5.5ns
Page Size
64Mbit
Memory Case Style
TSOP
No. Of Pins
86
Operating Temperature Range
0°C To +70°C
Frequency
166MHz
Supply Voltage
3.3V
Format - Memory
RAM
Memory Size
64M (2Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TFSOP (0.400", 10.16mm Width)
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC2M32B2P-6:G
Quantity:
106
Part Number:
MT48LC2M32B2P-6:G
Manufacturer:
MICRON
Quantity:
20 000
Figure 39:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
DQML, DQMH
Self Refresh Mode
COMMAND
A0–A9, A11
BA0, BA1
DQM/
Notes:
CLK
CKE
A10
DQ
High-Z
Precharge all
t CKS
t CMS
active banks
SINGLE BANK
t
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
1. No maximum time limit for self refresh mode.
2.
t CKH
t CMH
t
AH
t CK
t
XSR requires minimum of two clocks regardless of frequency and timing.
t RP
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
t RAS(MIN)
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54
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1
(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Exit self refresh mode
Tn + 1
NOP
t XSR
t
RAS(MAX) applies to non-self refresh mode.
(
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or COMMAND
INHIBIT
To + 1
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
To + 2
REFRESH
AUTO
Timing Diagrams
DON’T CARE

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